| 2008 |
|---|
| 6 | EE | Yuuri Sugihara,
Yohei Kume,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.
FPGA 2008: 257 |
| 5 | EE | Kazutoshi Kobayashi,
Yohei Kume,
Cam Lai Ngo,
Yuuri Sugihara,
Hidetoshi Onodera:
A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.
FPL 2008: 107-112 |
| 4 | EE | Yuuri Sugihara,
Yohei Kume,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.
FPL 2008: 503-506 |
| 2007 |
|---|
| 3 | EE | Yuuri Sugihara,
Manabu Kotani,
Kazuya Katsuki,
Kazutoshi Kobayashi,
Hidetoshi Onodera:
A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.
ASP-DAC 2007: 122-123 |
| 2 | EE | Kazutoshi Kobayashi,
Kazuya Katsuki,
Manabu Kotani,
Yuuri Sugihara,
Yohei Kume,
Hidetoshi Onodera:
A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.
IEICE Transactions 90-C(10): 1919-1926 (2007) |
| 2006 |
|---|
| 1 | EE | Kazutoshi Kobayashi,
Manabu Kotani,
Kazuya Katsuki,
Y. Takatsukasa,
K. Ogata,
Yuuri Sugihara,
Hidetoshi Onodera:
A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.
FPL 2006: 1-4 |
