Hiroki Matsutani

2009
17	EE	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga: Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378
2008
16	EE	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang: Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60
15	EE	Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi: A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274
14	EE	Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano: Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288
13	EE	Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston: A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22
12	EE	Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano: Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32
2007
11	EE	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388
10	EE	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75
9	EE	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10
8	EE	Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Transactions 90-D(12): 1914-1922 (2007)
2006
7		Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano: A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135
6		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. ISCA PDCS 2006: 24-31
5	EE	Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218
2005
4		Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima: An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. FPT 2005: 163-170
3	EE	Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai: Mobile Gateways for Mobile Ad-Hoc Networks with Network Mobility Support. ICN (2) 2005: 361-368
2	EE	Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku, Hideharu Amano: Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280
1		Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano: Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349

Coauthor Index

1	Shohei Abe	[4]
2	Hideharu Amano	[1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
3	Kenichiro Anjo	[4]
4	Toru Awashima	[4]
5	Yohei Hasegawa	[4]
6	D. Frank Hsu	[14]
7	Akiya Jouraku	[2]
8	Michihiro Koibuchi	[1] [2] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17]
9	Rajeev Koodli	[3]
10	Jun Murai	[3]
11	Anders Nilsson	[3]
12	Timothy Mark Pinkston	[13]
13	Ryuji Wakikawa	[3]
14	Daihan Wang	[7] [8] [11] [12] [15] [16]
15	Yutaka Yamada	[2]
16	Masato Yoshimi	[7]
17	Tsutomu Yoshinaga	[17]

Colors in the list of coauthors