2008 |
36 | EE | Josef Angermeier,
Mateusz Majer,
Jürgen Teich,
Lars Braun,
T. Schwalb,
Philipp Graf,
Michael Hübner,
Jürgen Becker,
Enno Lübbers,
Marco Platzner,
Christopher Claus,
Walter Stechele,
Andreas Herkersdorf,
Markus Rullmann,
Renate Merker:
Fine grain reconfigurable architectures.
FPL 2008: 348 |
2007 |
35 | EE | Markus Rullmann,
Renate Merker:
A Reconfiguration Aware Circuit Mapper for FPGAs.
IPDPS 2007: 1-8 |
34 | | Hritam Dutta,
Frank Hannig,
Alexey Kupriyanov,
Dmitrij Kissler,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach.
ReCoSoC 2007: 61-68 |
2006 |
33 | | Markus Rullmann,
Renate Merker:
Design and Implementation of Reconfigurable Tasks with Minimum Reconfiguration Overhead.
ARCS Workshops 2006: 132-141 |
32 | EE | Sebastian Siegel,
Renate Merker:
Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy.
ASAP 2006: 28-32 |
31 | EE | Sebastian Siegel,
Renate Merker:
Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints.
Euro-Par 2006: 1181-1191 |
30 | EE | Rainer Schaffer,
Renate Merker:
Parameterized Mapping of Algorithms onto Processor Arrays with Sub-Word Parallelism.
ICSAMOS 2006: 99-106 |
29 | EE | Markus Rullmann,
Renate Merker:
Maximum edge matching for reconfigurable computing.
IPDPS 2006 |
28 | EE | Rainer Schaffer,
Renate Merker,
Francky Catthoor:
Derivation of Packing Instructions for Exploiting Sub-Word Parallelism.
PARELEC 2006: 167-172 |
27 | EE | Sebastian Siegel,
Rainer Schaffer,
Renate Merker:
Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels.
PARELEC 2006: 173-180 |
2005 |
26 | EE | Markus Rullmann,
Sebastian Siegel,
Renate Merker:
Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching.
IPDPS 2005 |
25 | | Frank Hannig,
Hritam Dutta,
Alexey Kupriyanov,
Jürgen Teich,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Ronan Keryell,
Bernard Pottier,
Daniel Chillet,
Daniel Menard,
Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures.
ReCoSoC 2005: 27-34 |
2004 |
24 | EE | Sebastian Siegel,
Renate Merker:
Optimized Data-Reuse in Processor Arrays.
ASAP 2004: 315-325 |
23 | EE | Jan Müller,
Dirk Fimmel,
Renate Merker:
Optimal Loop Scheduling with Register Constraints Using Flow Graphs.
ISPAN 2004: 180-186 |
22 | EE | Jan Müller,
Dirk Fimmel,
Renate Merker:
Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling.
Interaction between Compilers and Computer Architectures 2004: 13-21 |
21 | EE | Mathias Kortke,
Jan Müller,
Rainer Schaffer,
Sebastian Siegel,
Renate Merker,
Jürgen Kelber:
A Parallel Hardware-Software System for Signal Processing Algorithms.
PARELEC 2004: 215-220 |
20 | EE | Sebastian Siegel,
Renate Merker:
Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays.
PARELEC 2004: 85-90 |
2003 |
19 | EE | Rainer Schaffer,
Renate Merker,
Francky Catthoor:
Causality Constraints for Processor Architectures with Sub-Word Parallelism.
DSD 2003: 82-89 |
18 | EE | Jan Müller,
Dirk Fimmel,
Renate Merker,
Rainer Schaffer:
A Hardware-Software System for Tomographic Reconstruction.
Journal of Circuits, Systems, and Computers 12(2): 203- (2003) |
2002 |
17 | EE | Rainer Schaffer,
Renate Merker,
Francky Catthoor:
Systematic Design of Programs with Sub-Word Parallelism.
PARELEC 2002: 393-398 |
2001 |
16 | | Dirk Fimmel,
Renate Merker:
Design of Processor Arrays for Reconfigurable Architectures.
The Journal of Supercomputing 19(1): 41-56 (2001) |
2000 |
15 | EE | Mathias Kortke,
Thomas Schmitt,
Renate Merker:
Application of Partitioning Methods for the Design of Parallel Programs for a System of Digital Signal Processors.
PARELEC 2000: 139-143 |
14 | EE | Renate Merker:
High-Level Synthesis System (HLDESA) for Processor Arrays.
PARELEC 2000: 89-93 |
13 | EE | Rainer Schaffer,
Renate Merker,
Francky Catthoor:
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.
VLSI Design 2000: 104-109 |
12 | | Rainer Schaffer,
Francky Catthoor,
Renate Merker:
Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.
Parallel Algorithms Appl. 15(3-4): 201-228 (2000) |
1999 |
11 | | Thomas Schmitt,
Dirk Fimmel,
Mathias Kortke,
Renate Merker:
Parallel Processor Array for Tomographic Reconstruction Algorithms.
EUROCAST 1999: 127-141 |
10 | EE | Mathias Kortke,
Dirk Fimmel,
Renate Merker:
Parallelization of Algorithms for a System of Digital Signal Processors.
EUROMICRO 1999: 1046-1050 |
9 | EE | Dirk Fimmel,
Renate Merker:
Localization of Data Transfer in Processor Arrays.
Euro-Par 1999: 401-408 |
8 | EE | Uwe Eckhardt,
Renate Merker:
Hierarchical algorithm partitioning at system level for an improved utilization of memory structures.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 14-24 (1999) |
1998 |
7 | EE | Dirk Fimmel,
Renate Merker:
Design of Processor Arrays for Real-Time Applications.
Euro-Par 1998: 1018-1028 |
1997 |
6 | EE | Dirk Fimmel,
Renate Merker:
Determination of the Processor Functionality in the Design of Processor Arrays.
ASAP 1997: 199-208 |
5 | EE | Uwe Eckhardt,
Renate Merker:
Scheduling in Co-Partitioned Array Architectures.
ASAP 1997: 219-228 |
4 | | Renate Merker,
Ulrich Eckhardt,
Dirk Fimmel,
H. Schreiber:
A System for Designing Parallel Processor Arrays.
EUROCAST 1997: 3-12 |
3 | EE | Uwe Eckhardt,
Renate Merker:
Optimization of the Background Memory Utilization by Partitioning.
ISSS 1997: 82-89 |
1996 |
2 | EE | Dirk Fimmel,
Renate Merker:
Propagation of I/O-Variables in Massively Parallel Processor Arrays.
PDP 1996: 501-509 |
1994 |
1 | | A. Schubert,
Renate Merker,
H. Schreiber:
Systematic Generation of a Variety of Processor Arrays.
Parcella 1994: 267-276 |