| 2009 |
|---|
| 91 | EE | Abhishek Mitra,
Marcos R. Vieira,
Petko Bakalov,
Vassilis J. Tsotras,
Walid A. Najjar:
Boosting XML filtering through a scalable FPGA-based architecture.
CIDR 2009 |
| 90 | EE | Dinesh C. Suresh,
Banit Agrawal,
Jun Yang,
Walid A. Najjar:
Energy-efficient encoding techniques for off-chip data buses.
ACM Trans. Embedded Comput. Syst. 8(2): (2009) |
| 2008 |
|---|
| 89 | EE | Betul Buyukkurt,
Walid A. Najjar:
Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs.
FPL 2008: 655-658 |
| 88 | EE | Jason R. Villarreal,
Walid A. Najjar:
Compiled hardware acceleration of Molecular Dynamics code.
FPL 2008: 667-670 |
| 87 | EE | Zhi Guo,
Betul Buyukkurt,
John Cortes,
Abhishek Mitra,
Walid A. Najjar:
A Compiler Intermediate Representation for Reconfigurable Fabrics.
International Journal of Parallel Programming 36(5): 493-520 (2008) |
| 86 | EE | Michael J. Wirthlin,
Daniel S. Poznanovic,
P. Sundararajan,
Alan J. Coppola,
D. Pellerin,
Walid A. Najjar,
R. Bruce,
M. Babst,
O. Pritchard,
Paolo Palazzari,
Georgi Kuzmanov:
OpenFPGA CoreLib core library interoperability effort.
Parallel Computing 34(4-5): 231-244 (2008) |
| 85 | EE | Michael J. Wirthlin,
Daniel S. Poznanovic,
P. Sundararajan,
Alan J. Coppola,
D. Pellerin,
Walid A. Najjar,
R. Bruce,
M. Babst,
O. Pritchard,
Paolo Palazzari,
Georgi Kuzmanov:
OpenFPGA CoreLib core library interoperability effort.
Parallel Computing 34(4-5): 231-244 (2008) |
| 84 | EE | Zhi Guo,
Walid A. Najjar,
Betul Buyukkurt:
Efficient hardware code generation for FPGAs.
TACO 5(1): (2008) |
| 2007 |
|---|
| 83 | | Koen Bertels,
Walid A. Najjar,
Arjan J. van Genderen,
Stamatis Vassiliadis:
FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007
IEEE 2007 |
| 82 | EE | Abhishek Mitra,
Walid A. Najjar,
Laxmi N. Bhuyan:
Compiling PCRE to FPGA for accelerating SNORT IDS.
ANCS 2007: 127-136 |
| 81 | EE | Walid A. Najjar:
Compiling code accelerators for FPGAs.
CASES 2007: 1-2 |
| 80 | EE | Walid A. Najjar:
Compiling code accelerators for FPGAs.
CODES+ISSS 2007: 2 |
| 79 | EE | Ann Gordon-Ross,
Pablo Viana,
Frank Vahid,
Walid A. Najjar,
Edna Barros:
A one-shot configurable-cache tuner for improved energy and performance.
DATE 2007: 755-760 |
| 78 | EE | Kai Schleupen,
Scott Lekuch,
Ryan Mannion,
Zhi Guo,
Walid A. Najjar,
Frank Vahid:
Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System.
FPL 2007: 533-536 |
| 77 | EE | Zhi Guo,
Betul Buyukkurt,
Walid A. Najjar,
Kees A. Vissers:
Optimized Generation of Data-Path from C Codes for FPGAs
CoRR abs/0710.4716: (2007) |
| 2006 |
|---|
| 76 | EE | Betul Buyukkurt,
Zhi Guo,
Walid A. Najjar:
Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs.
ARC 2006: 401-412 |
| 75 | EE | Dinesh C. Suresh,
Zhi Guo,
Betul Buyukkurt,
Walid A. Najjar:
Automatic Compilation Framework for Bloom Filter Based Intrusion Detection.
ARC 2006: 413-418 |
| 74 | EE | Zhi Guo,
Walid A. Najjar:
A Compiler Intermediate Representation for Reconfigurable Fabrics.
FPL 2006: 1-4 |
| 73 | EE | Zhi Guo,
Abhishek Mitra,
Walid A. Najjar:
Automation of IP Core Interface Generation for Reconfigurable Computing.
FPL 2006: 1-6 |
| 72 | EE | Greg Stitt,
Frank Vahid,
Walid A. Najjar:
A code refinement methodology for performance-improved synthesis from C.
ICCAD 2006: 716-723 |
| 71 | EE | Abhishek Mitra,
Zhi Guo,
Anirban Banerjee,
Walid A. Najjar:
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs.
ICCD 2006 |
| 70 | EE | Dhananjay Kulkarni,
Walid A. Najjar,
Robert Rinker,
Fadi J. Kurdahi:
Compile-time area estimation for LUT-based FPGAs.
ACM Trans. Design Autom. Electr. Syst. 11(1): 104-122 (2006) |
| 69 | EE | Song Lin,
Demetrios Zeinalipour-Yazti,
Vana Kalogeraki,
Dimitrios Gunopulos,
Walid A. Najjar:
Efficient indexing data structures for flash-based sensor devices.
TOS 2(4): 468-503 (2006) |
| 2005 |
|---|
| 68 | | Thomas M. Conte,
Paolo Faraboschi,
William H. Mangione-Smith,
Walid A. Najjar:
Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005
ACM 2005 |
| 67 | EE | Zhi Guo,
Betul Buyukkurt,
Walid A. Najjar,
Kees A. Vissers:
Optimized Generation of Data-Path from C Codes for FPGAs.
DATE 2005: 112-117 |
| 66 | EE | Demetrios Zeinalipour-Yazti,
Song Lin,
Vana Kalogeraki,
Dimitrios Gunopulos,
Walid A. Najjar:
MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices.
FAST 2005 |
| 65 | EE | Greg Stitt,
Zhi Guo,
Walid A. Najjar,
Frank Vahid:
Techniques for synthesizing binaries to an advanced register/memory structure.
FPGA 2005: 118-124 |
| 64 | EE | Dinesh C. Suresh,
Banit Agrawal,
Walid A. Najjar,
Jun Yang:
VALVE: Variable Length Value Encoder for Off-Chip Data Buses..
ICCD 2005: 631-633 |
| 63 | EE | Demetrios Zeinalipour-Yazti,
Vana Kalogeraki,
Dimitrios Gunopulos,
Walid A. Najjar:
Data Acquisition in Sensor Networks with Large Memories.
ICDE Workshops 2005: 1188 |
| 62 | EE | Dinesh C. Suresh,
Banit Agrawal,
Jun Yang,
Walid A. Najjar:
A tunable bus encoder for off-chip data buses.
ISLPED 2005: 319-322 |
| 61 | EE | Demetrios Zeinalipour-Yazti,
Vana Kalogeraki,
Dimitrios Gunopulos,
Anirban Mitra,
Anirban Banerjee,
Walid A. Najjar:
Towards In-Situ Data Storage in Sensor Databases.
Panhellenic Conference on Informatics 2005: 36-46 |
| 60 | EE | Dinesh C. Suresh,
Walid A. Najjar,
Jun Yang:
Power Efficient Instruction Caches for Embedded Systems.
SAMOS 2005: 182-191 |
| 59 | EE | Anirban Banerjee,
Anirban Mitra,
Walid A. Najjar:
Splitting the sensor node.
SenSys 2005: 270-271 |
| 58 | EE | Chuanjun Zhang,
Frank Vahid,
Walid A. Najjar:
A highly configurable cache for low energy embedded systems.
ACM Trans. Embedded Comput. Syst. 4(2): 363-387 (2005) |
| 57 | EE | Chuanjun Zhang,
Frank Vahid,
Jun Yang,
Walid A. Najjar:
A way-halting cache for low-energy high-performance systems.
TACO 2(1): 34-54 (2005) |
| 2004 |
|---|
| 56 | | Walid A. Najjar:
From Here to Main-stream: The Present and Future of Reconfigurable Computing.
ERSA 2004: 17 |
| 55 | EE | Zhi Guo,
Walid A. Najjar,
Frank Vahid,
Kees A. Vissers:
A quantitative analysis of the speedup factors of FPGAs over processors.
FPGA 2004: 162-170 |
| 54 | EE | Walid A. Najjar:
"How Long is Your Belt?" Towards a Single Device for Multiple Functions.
ICPS 2004: 19-19 |
| 53 | EE | Chuanjun Zhang,
Frank Vahid,
Jun Yang,
Walid A. Najjar:
A way-halting cache for low-energy high-performance systems.
ISLPED 2004: 126-131 |
| 52 | EE | Zhi Guo,
Betul Buyukkurt,
Walid A. Najjar:
Input data reuse in compiling window operations onto reconfigurable hardware.
LCTES 2004: 249-256 |
| 2003 |
|---|
| 51 | EE | Dinesh C. Suresh,
Banit Agrawal,
Jun Yang,
Walid A. Najjar,
Laxmi N. Bhuyan:
Power efficient encoding techniques for off-chip data buses.
CASES 2003: 267-275 |
| 50 | EE | Susan Cotterell,
Frank Vahid,
Walid A. Najjar,
Harry Hsieh:
First results with eBlocks: embedded systems building blocks.
CODES+ISSS 2003: 168-175 |
| 49 | EE | Dinesh C. Suresh,
Jun Yang,
Chuanjun Zhang,
Banit Agrawal,
Walid A. Najjar:
FV-MSB: A Scheme for Reducing Transition Activity on Data Buses.
HiPC 2003: 44-54 |
| 48 | EE | Chuanjun Zhang,
Frank Vahid,
Walid A. Najjar:
A Highly-Configurable Cache Architecture for Embedded Systems.
ISCA 2003: 136-146 |
| 47 | EE | Chuanjun Zhang,
Frank Vahid,
Walid A. Najjar:
Energy Benefits of a Configurable Line Size Cache for Embedded Systems.
ISVLSI 2003: 87-91 |
| 46 | EE | Dinesh C. Suresh,
Walid A. Najjar,
Frank Vahid,
Jason R. Villarreal,
Greg Stitt:
Profiling tools for hardware/software partitioning of embedded applications.
LCTES 2003: 189-198 |
| 45 | EE | Girish Venkataramani,
Walid A. Najjar,
Fadi J. Kurdahi,
Nader Bagherzadeh,
A. P. Wim Böhm,
Jeffrey Hammes:
Automatic compilation to a coarse-grained reconfigurable system-opn-chip.
ACM Trans. Embedded Comput. Syst. 2(4): 560-589 (2003) |
| 44 | EE | Chuanjun Zhang,
Frank Vahid,
Jun Yang,
Walid A. Najjar:
A Way-Halting Cache for Low-Energy High-Performance Systems.
Computer Architecture Letters 2: (2003) |
| 43 | EE | Walid A. Najjar,
A. P. Wim Böhm,
Bruce A. Draper,
Jeffrey Hammes,
Robert Rinker,
J. Ross Beveridge,
Monica Chawathe,
Charles Ross:
High-Level Language Abstraction for Reconfigurable Computing.
IEEE Computer 36(8): 63-69 (2003) |
| 2002 |
|---|
| 42 | EE | Dhananjay Kulkarni,
Walid A. Najjar,
Robert Rinker,
Fadi J. Kurdahi:
Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems.
FCCM 2002: 239- |
| 41 | EE | A. P. Wim Böhm,
J. Ross Beveridge,
Bruce A. Draper,
Charlie Ross,
Monica Chawathe,
Walid A. Najjar:
Compiling ATR Probing Codes for Execution on FPGA Hardware.
FCCM 2002: 301-302 |
| 40 | | A. P. Wim Böhm,
Jeffrey Hammes,
Bruce A. Draper,
Monica Chawathe,
Charlie Ross,
Robert Rinker,
Walid A. Najjar:
Mapping a Single Assignment Programming Language to Reconfigurable Systems.
The Journal of Supercomputing 21(2): 117-130 (2002) |
| 2001 |
|---|
| 39 | EE | Girish Venkataramani,
Walid A. Najjar,
Fadi J. Kurdahi,
Nader Bagherzadeh,
A. P. Wim Böhm:
A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture.
CASES 2001: 116-125 |
| 38 | EE | Jean-Luc Gaudiot,
Thomas DeBoni,
John Feo,
A. P. Wim Böhm,
Walid A. Najjar,
Patrick Miller:
The Sisal Project: Real World Functional Programming.
Compiler Optimizations for Scalable Parallel Systems Languages 2001: 45-72 |
| 37 | EE | Bruce A. Draper,
A. P. Wim Böhm,
Jeffrey Hammes,
Walid A. Najjar,
J. Ross Beveridge,
Charlie Ross,
Monica Chawathe,
Mitesh Desai,
José Bins:
Compiling SA-C Programs to FPGAs: Performance Results.
ICVS 2001: 220-235 |
| 36 | | Jeffrey Hammes,
A. P. Wim Böhm,
Charlie Ross,
Monica Chawathe,
Bruce A. Draper,
Robert Rinker,
Walid A. Najjar:
Loop fusion and temporal common subexpression elimination in window-based loops.
IPDPS 2001: 142 |
| 35 | | Dianne R. Kumar,
Walid A. Najjar,
Pradip K. Srimani:
Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubes.
IPDPS 2001: 160 |
| 34 | EE | Dianne R. Kumar,
Walid A. Najjar,
Pradip K. Srimani:
A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes.
IEEE Trans. Computers 50(7): 647-659 (2001) |
| 33 | EE | Robert Rinker,
M. Carter,
A. Patel,
Monica Chawathe,
Charlie Ross,
Jeffrey Hammes,
Walid A. Najjar,
A. P. Wim Böhm:
An automated process for compiling dataflow graphs into reconfigurable hardware.
IEEE Trans. VLSI Syst. 9(1): 130-139 (2001) |
| 32 | EE | Lucas Roh,
Bhanu Shankar,
A. P. Wim Böhm,
Walid A. Najjar:
Resource Management in Dataflow-Based Multithreaded Execution.
J. Parallel Distrib. Comput. 61(5): 581-608 (2001) |
| 2000 |
|---|
| 31 | EE | Robert Rinker,
Jeffrey Hammes,
Walid A. Najjar,
A. P. Wim Böhm,
Bruce A. Draper:
Compiling Image Processing Applications to Reconfigurable Hardware.
ASAP 2000: 56-65 |
| 30 | EE | Bruce A. Draper,
Walid A. Najjar,
A. P. Wim Böhm,
Jeffrey Hammes,
Robert Rinker,
Charlie Ross,
Monica Chawathe,
José Bins:
Compiling and Optimizing Image Processing Algorithms for FPGAs.
CAMP 2000: 222-231 |
| 29 | | Jeffrey Hammes,
Robert Rinker,
A. P. Wim Böhm,
Walid A. Najjar,
Bruce A. Draper:
A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems.
PDPTA 2000 |
| 1999 |
|---|
| 28 | | Dianne R. Kumar,
Walid A. Najjar:
Combining Adaptive and Deterministic Routing: Evaluation of a Hybrid Router.
CANPC 1999: 150-164 |
| 27 | EE | Jeffrey Hammes,
Robert Rinker,
A. P. Wim Böhm,
Walid A. Najjar,
Bruce A. Draper,
J. Ross Beveridge:
Cameron: High level Language Compilation for Reconfigurable Systems.
IEEE PACT 1999: 236-244 |
| 26 | | Walid A. Najjar,
Edward A. Lee,
Guang R. Gao:
Advances in the dataflow computational model.
Parallel Computing 25(13-14): 1907-1929 (1999) |
| 1997 |
|---|
| 25 | EE | Dianne Miller,
Walid A. Najjar:
Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area Routers.
IEEE PACT 1997: 64- |
| 24 | EE | Dianne Miller,
Walid A. Najjar:
Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router.
PCRCW 1997: 89-102 |
| 1996 |
|---|
| 23 | | Annette Lagman,
Walid A. Najjar:
Analysis of Buffer Design for Adaptive Routing in Direct Networks.
MASCOTS 1996: 134-139 |
| 22 | | Lucas Roh,
Walid A. Najjar,
Bhanu Shankar,
A. P. Wim Böhm:
Generation, Optimization, and Evaluation of Multithreaded Code.
J. Parallel Distrib. Comput. 32(2): 188-204 (1996) |
| 1995 |
|---|
| 21 | EE | Lucas Roh,
Walid A. Najjar:
Design of storage hierarchy in multithreaded architectures.
MICRO 1995: 271-278 |
| 20 | | William Marcus Miller,
Walid A. Najjar,
A. P. Wim Böhm:
Exploiting Data Structure Locality in the Dataflow Model.
J. Parallel Distrib. Comput. 27(2): 183-200 (1995) |
| 1994 |
|---|
| 19 | | Lucas Roh,
Walid A. Najjar,
Bhanu Shankar,
A. P. Wim Böhm:
An Evaluation of Optimized Threaded Code Generation.
IFIP PACT 1994: 37-46 |
| 18 | EE | William Marcus Miller,
Walid A. Najjar,
A. P. Wim Böhm:
A model for dataflow based vector execution.
International Conference on Supercomputing 1994: 11-22 |
| 17 | | Walid A. Najjar,
Annette Lagman,
Sumit Sur,
Pradip K. Srimani:
Modeling Adaptive Routing in k-ary n-cube Networks.
MASCOTS 1994: 120-125 |
| 16 | | Walid A. Najjar,
Jean-Luc Gaudiot:
Authors' Reply.
IEEE Trans. Computers 43(12): 1452-1453 (1994) |
| 15 | | Annette Lagman,
Walid A. Najjar,
Pradip K. Srimani:
An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks.
IEEE Trans. Computers 43(4): 470-475 (1994) |
| 1993 |
|---|
| 14 | | Walid A. Najjar,
Lucas Roh,
A. P. Wim Böhm:
The Initial Performance of a Bottom-Up Clustering Algorithm for Dataflow Graphs.
Architectures and Compilation Techniques for Fine and Medium Grain Parallelism 1993: 91-100 |
| 13 | | Lucas Roh,
Walid A. Najjar,
A. P. Wim Böhm:
Generation and Quantitative Evaluation of Dataflow Clusters.
FPCA 1993: 159-168 |
| 12 | EE | A. P. Wim Böhm,
Walid A. Najjar,
Bhanu Shankar,
Lucas Roh:
An evaluation of bottom-up and top-down thread generation techniques.
MICRO 1993: 118-127 |
| 11 | | Annette Lagman,
Walid A. Najjar,
Sumit Sur,
Pradip K. Srimani:
Evaluation of Idealized Adaptive Routing on k-ary n-cubes.
SPDP 1993: 166-169 |
| 10 | | Walid A. Najjar,
A. P. Wim Böhm,
William Marcus Miller:
A Quantitative Analysis of Dataflow Program Execution - Preliminaries to a Hybrid Design.
J. Parallel Distrib. Comput. 18(3): 314-326 (1993) |
| 1992 |
|---|
| 9 | | Walid A. Najjar,
William Marcus Miller,
A. P. Wim Böhm:
An Analysis of Loop Latency in Dataflow Execution.
ISCA 1992: 352-360 |
| 1991 |
|---|
| 8 | EE | William Marcus Miller,
Walid A. Najjar,
A. P. Wim Böhm:
A Quantitative Analysis of Locality in Dataflow Programs.
MICRO 1991: 12-18 |
| 1990 |
|---|
| 7 | EE | Walid A. Najjar,
Jean-Luc Gaudiot:
A data-driven execution paradigm for distributed fault-tolerance.
ACM SIGOPS European Workshop 1990 |
| 6 | | Walid A. Najjar,
Jean-Luc Gaudiot:
Network Resilience: A Measure of Network Fault Tolerance.
IEEE Trans. Computers 39(2): 174-181 (1990) |
| 1989 |
|---|
| 5 | | Paraskevas Evripidou,
Walid A. Najjar,
Jean-Luc Gaudiot:
A Single-Assignment Language in a Distributed Memory Multiprocessor.
PARLE (2) 1989: 304-320 |
| 4 | | Walid A. Najjar,
Jean-Luc Gaudiot:
Limits on Scalability in Gracefully Degradable Large-Scale Systems.
SRDS 1989: 148-157 |
| 1988 |
|---|
| 3 | | Walid A. Najjar,
Jean-Luc Gaudiot:
Network Disconnection in Distributed Systems.
ICDCS 1988: 554-561 |
| 1987 |
|---|
| 2 | | Walid A. Najjar,
Jean-Luc Gaudiot:
Reliability and Performance Modelling of Hypercube-Based Mutliprocessors.
Computer Performance and Reliability 1987: 305-320 |
| 1 | | Walid A. Najjar,
Jean-Luc Gaudiot:
Multi-Level Execution In Data-Flow Architectures.
ICPP 1987: 32-39 |
