2008 |
30 | EE | Akashi Satoh,
Takeshi Sugawara,
Naofumi Homma,
Takafumi Aoki:
High-Performance Concurrent Error Detection Scheme for AES Hardware.
CHES 2008: 100-112 |
29 | EE | Naofumi Homma,
Atsushi Miyamoto,
Takafumi Aoki,
Akashi Satoh,
Adi Shamir:
Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs.
CHES 2008: 15-29 |
28 | EE | Atsushi Miyamoto,
Naofumi Homma,
Takafumi Aoki,
Akashi Satoh:
Chosen-message SPA attacks against FPGA-based RSA hardware implementations.
FPL 2008: 35-40 |
27 | EE | Atsushi Miyamoto,
Naofumi Homma,
Takafumi Aoki,
Akashi Satoh:
Systematic design of high-radix Montgomery multipliers for RSA processors.
ICCD 2008: 416-421 |
26 | EE | Yuki Watanabe,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Arithmetic module generator with algorithm optimization capability.
ISCAS 2008: 1796-1799 |
25 | EE | Takeshi Sugawara,
Naofumi Homma,
Takafumi Aoki,
Akashi Satoh:
High-performance ASIC implementations of the 128-bit block cipher CLEFIA.
ISCAS 2008: 2925-2928 |
24 | EE | Atsushi Miyamoto,
Naofumi Homma,
Takafumi Aoki,
Akashi Satoh:
Enhanced power analysis attack using chosen message against RSA hardware implementations.
ISCAS 2008: 3282-3285 |
23 | EE | Yuki Watanabe,
Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
ISMVL 2008: 112-117 |
22 | EE | Takeshi Sugawara,
Naofumi Homma,
Takafumi Aoki,
Akashi Satoh:
Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool.
WISA 2008: 28-40 |
21 | EE | Naofumi Homma,
T. Aoki,
Tatsuo Higuchi:
A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams.
IEEE Trans. Computers 57(12): 1633-1646 (2008) |
20 | EE | Naofumi Homma,
Sei Nagashima,
Takeshi Sugawara,
Takafumi Aoki,
Akashi Satoh:
A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks.
IEICE Transactions 91-A(1): 193-202 (2008) |
2007 |
19 | EE | Yuki Watanabe,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Application of symbolic computer algebra to arithmetic circuit verification.
ICCD 2007: 25-32 |
18 | EE | Sei Nagashima,
Naofumi Homma,
Yuichi Imai,
Takafumi Aoki,
Akashi Satoh:
DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure.
ISCAS 2007: 1807-1810 |
17 | EE | Atsushi Miyamoto,
Naofumi Homma,
Takafumi Aoki,
Akashi Satoh:
SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier.
ISCAS 2007: 1847-1850 |
16 | EE | Takeshi Sugawara,
Naofumi Homma,
Takafumi Aoki,
Akashi Satoh:
A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128.
ISCAS 2007: 1859-1862 |
15 | EE | Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.
ISMVL 2007: 31 |
2006 |
14 | EE | Naofumi Homma,
Sei Nagashima,
Yuichi Imai,
Takafumi Aoki,
Akashi Satoh:
High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching.
CHES 2006: 187-200 |
13 | EE | Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic.
ISMVL 2006: 2 |
12 | EE | Naofumi Homma,
Yuki Watanabe,
Takafumi Aoki,
Tatsuo Higuchi:
Formal Design of Arithmetic Circuits Based on Arithmetic Description Language.
IEICE Transactions 89-A(12): 3500-3509 (2006) |
11 | EE | Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic.
IEICE Transactions 89-C(11): 1645-1654 (2006) |
2004 |
10 | EE | Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Multiplier Block Synthesis Using Evolutionary Graph Generation.
Evolvable Hardware 2004: 79-82 |
9 | | Naofumi Homma,
Jun Sakiyama,
Taihei Wakamatsu,
Takafumi Aoki,
Tatsuo Higuchi:
A systematic approach for analyzing fast addition algorithms using counter tree diagrams.
ISCAS (5) 2004: 197-200 |
8 | EE | Kazuya Ishida,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH.
ISMVL 2004: 334-339 |
7 | EE | Masanori Natsui,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation.
PPSN 2004: 342-351 |
2003 |
6 | EE | Naofumi Homma,
Masanori Natsui,
Takafumi Aoki,
Tatsuo Higuchi:
VLSI circuit design using an object-oriented framework of evolutionary graph generation system.
IEEE Congress on Evolutionary Computation (1) 2003: 115-122 |
5 | EE | Naofumi Homma,
Takafumi Aoki,
Makoto Motegi,
Tatsuo Higuchi:
A framework of evolutionary graph generation system and its application to circuit synthesis.
ISCAS (5) 2003: 201-204 |
4 | EE | Takafumi Aoki,
Naofumi Homma,
Tatsuo Higuchi:
Evolutionary Synthesis of Arithmetic Circuit Structures.
Artif. Intell. Rev. 20(3-4): 199-232 (2003) |
2002 |
3 | EE | Makoto Motegi,
Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis.
PPSN 2002: 831-840 |
2 | | Dingjun Chen,
Takafumi Aoki,
Naofumi Homma,
Toshiki Terasaki,
Tatsuo Higuchi:
Graph-based evolutionary design of arithmetic circuits.
IEEE Trans. Evolutionary Computation 6(1): 86-100 (2002) |
2001 |
1 | EE | Naofumi Homma,
Takafumi Aoki,
Tatsuo Higuchi:
Evolutionary graph generation system with transmigration capability for arithmetic circuit design.
ISCAS (5) 2001: 171-174 |