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Frank Hannig

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2009
31EEFrank Hannig, Hritam Dutta, Jürgen Teich: Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27
30EEHritam Dutta, Frank Hannig, Jürgen Teich: Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245
2008
29EEFrank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich: PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289
28EEChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Optimization of Routing and Reconfiguration Overhead in Programmable Processor Array Architectures. FCCM 2008: 306-309
27EESven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349
26EEChristophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig: Area and reconfiguration time minimization of the communication network in regular 2D reconfigurable architectures. FPL 2008: 391-396
25EEDmitrij Kissler, Andreas Strawetz, Frank Hannig, Jürgen Teich: Power-Efficient Reconfiguration Control in Coarse-Grained Dynamically Reconfigurable Architectures. PATMOS 2008: 307-317
2007
24EEAlexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement: Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282
23 Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet: A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24
22 Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier: Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68
21EEAlexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich: Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80
20EEHritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich: Efficient control generation for mapping nested loop programs onto processor arrays. Journal of Systems Architecture 53(5-6): 300-309 (2007)
2006
19EEHritam Dutta, Frank Hannig, Jürgen Teich: Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190
18EEHritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger: A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340
17 Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich: A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195
16EEHritam Dutta, Frank Hannig, Jürgen Teich: Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160
15 Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich: A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37
14EEFrank Hannig, Hritam Dutta, Jürgen Teich: Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. IJES 2(1/2): 114-127 (2006)
2005
13EEThomas Schlichter, Christian Haubelt, Frank Hannig, Jürgen Teich: Using Symbolic Feasibility Tests during Design Space Exploration of Heterogeneous Multi-Processor Systems. ASAP 2005: 9-14
12 Frank Hannig, Jürgen Teich: Output Serialization for FPGA-based and Coarse-grained Processor Arrays. ERSA 2005: 78-84
11 Jan van der Veen, Sándor P. Fekete, Mateusz Majer, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device. ERSA 2005: 92-104
10 Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34
9EEHolger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich: Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61
8EEJan van der Veen, Sándor P. Fekete, Ali Ahmadinia, Christophe Bobda, Frank Hannig, Jürgen Teich: Defragmenting the Module Layout of a Partially Reconfigurable Device CoRR abs/cs/0505005: (2005)
2004
7EEFrank Hannig, Jürgen Teich: Resource Constrained and Speculative Scheduling of an Algorithm Class with Run-Time Dependent Conditionals. ASAP 2004: 17-27
6EEFrank Hannig, Hritam Dutta, Jürgen Teich: Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004
5EEFrank Hannig, Jürgen Teich: Dynamic Piecewise Linear/Regular Algorithms. PARELEC 2004: 79-84
4EEAlexey Kupriyanov, Frank Hannig, Jürgen Teich: High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529
2002
3EEMarcus Bednara, Frank Hannig, Jürgen Teich: Generation of Distributed Loop Control. Embedded Processor Design Challenges 2002: 154-170
2EEFrank Hannig, Jürgen Teich: Energy estimation of nested loop programs. SPAA 2002: 149-150
2001
1EEFrank Hannig, Jürgen Teich: Design Space Exploration for Massively Parallel Processor Arrays. PaCT 2001: 51-65

Coauthor Index

1Ali Ahmadinia [8] [11]
2Jürgen Becker [27]
3Marcus Bednara [3]
4Christophe Bobda [8] [11]
5Daniel Chillet [10]
6Hritam Dutta [6] [9] [10] [14] [16] [18] [19] [20] [22] [23] [27] [29] [30] [31]
7Sven Eisenhardt [27]
8Sándor P. Fekete [8] [11]
9Julio A. de Oliveira Filho [27]
10Manfred Glesner [27]
11Christian Haubelt [13]
12Benno Heigl [18]
13Heiko Hinkelmann [27]
14Heinz Hornegger [18]
15Ronan Keryell [10]
16Dmitrij Kissler [15] [17] [21] [22] [23] [24] [25] [27]
17Dirk Koch [17]
18Krzysztof Kuchcinski [26] [28]
19Alexey Kupriyanov [4] [10] [15] [17] [21] [22] [24]
20Julien Lallet [24]
21Mateusz Majer [11]
22Daniel Menard [10]
23Renate Merker [10] [22]
24Tobias Oppold [27]
25Sébastien Pillement [24]
26Bernard Pottier [10] [22]
27Wolfgang Rosenstiel [27]
28Holger Ruckdeschel [9] [20] [23] [29]
29Rainer Schaffer [10] [22]
30Thomas Schlichter [13]
31Thomas Schweizer [27]
32Olivier Sentieys [10] [24]
33Sebastian Siegel [10] [22]
34Andrej Stravet [23]
35Andreas Strawetz [25]
36Jürgen Teich [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
37Alexander Thomas [27]
38Jan van der Veen [8] [11]
39Christophe Wolinski [26] [28]
40Peter Zipf [27]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)