Hritam Dutta

2009
14	EE	Frank Hannig, Hritam Dutta, Jürgen Teich: Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning. ARCS 2009: 16-27
13	EE	Hritam Dutta, Frank Hannig, Jürgen Teich: Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis. ARCS 2009: 233-245
2008
12	EE	Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich: PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications. ARC 2008: 284-289
11	EE	Sven Eisenhardt, Thomas Schweizer, Julio A. de Oliveira Filho, Tobias Oppold, Wolfgang Rosenstiel, Alexander Thomas, Jürgen Becker, Frank Hannig, Dmitrij Kissler, Hritam Dutta, Jürgen Teich, Heiko Hinkelmann, Peter Zipf, Manfred Glesner: Coarse-grained reconfiguration. FPL 2008: 349
2007
10		Jürgen Teich, Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Dmitrij Kissler, Andrej Stravet: A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays: Case Study and Quantitative Evaluation. ERSA 2007: 14-24
9		Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier: Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68
8	EE	Hritam Dutta, Frank Hannig, Holger Ruckdeschel, Jürgen Teich: Efficient control generation for mapping nested loop programs onto processor arrays. Journal of Systems Architecture 53(5-6): 300-309 (2007)
2006
7	EE	Hritam Dutta, Frank Hannig, Jürgen Teich: Controller Synthesis for Mapping Partitioned Programs on Array Architectures. ARCS 2006: 176-190
6	EE	Hritam Dutta, Frank Hannig, Jürgen Teich, Benno Heigl, Heinz Hornegger: A Design Methodology for Hardware Acceleration of Adaptive Filter Algorithms in Image Processing. ASAP 2006: 331-340
5	EE	Hritam Dutta, Frank Hannig, Jürgen Teich: Hierarchical Partitioning for Piecewise Linear Algorithms. PARELEC 2006: 153-160
4	EE	Frank Hannig, Hritam Dutta, Jürgen Teich: Mapping a class of dependence algorithms to coarse-grained reconfigurable arrays: architectural parameters and methodology. IJES 2(1/2): 114-127 (2006)
2005
3		Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34
2	EE	Holger Ruckdeschel, Hritam Dutta, Frank Hannig, Jürgen Teich: Automatic FIR Filter Generation for FPGAs. SAMOS 2005: 51-61
2004
1	EE	Frank Hannig, Hritam Dutta, Jürgen Teich: Mapping of Regular Nested Loop Programs to Coarse-Grained Reconfigurable Arrays - Constraints and Methodology. IPDPS 2004

Coauthor Index

1	Jürgen Becker	[11]
2	Daniel Chillet	[3]
3	Sven Eisenhardt	[11]
4	Julio A. de Oliveira Filho	[11]
5	Manfred Glesner	[11]
6	Frank Hannig	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
7	Benno Heigl	[6]
8	Heiko Hinkelmann	[11]
9	Heinz Hornegger	[6]
10	Ronan Keryell	[3]
11	Dmitrij Kissler	[9] [10] [11]
12	Alexey Kupriyanov	[3] [9]
13	Daniel Menard	[3]
14	Renate Merker	[3] [9]
15	Tobias Oppold	[11]
16	Bernard Pottier	[3] [9]
17	Wolfgang Rosenstiel	[11]
18	Holger Ruckdeschel	[2] [8] [10] [12]
19	Rainer Schaffer	[3] [9]
20	Thomas Schweizer	[11]
21	Olivier Sentieys	[3]
22	Sebastian Siegel	[3] [9]
23	Andrej Stravet	[10]
24	Jürgen Teich	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
25	Alexander Thomas	[11]
26	Peter Zipf	[11]