| 2008 |
|---|
| 10 | EE | Anh Tuan Hoang,
Katsuhiro Yamazaki,
Shigeru Oyanagi:
Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding.
FCCM 2008: 271-272 |
| 9 | EE | Anh Tuan Hoang,
Katsuhiro Yamazaki,
Shigeru Oyanagi:
Three-stage pipeline implementation for SHA2 using data forwarding.
FPL 2008: 29-34 |
| 2006 |
|---|
| 8 | EE | Tran Minh Quang,
Shigeru Oyanagi,
Katsuhiro Yamazaki:
ExMiner: An Efficient Algorithm for Mining Top-K Frequent Patterns.
ADMA 2006: 436-447 |
| 7 | EE | Tran Minh Quang,
Shigeru Oyanagi,
Katsuhiro Yamazaki:
Mining the K-Most Interesting Frequent Patterns Sequentially.
IDEAL 2006: 620-628 |
| 2002 |
|---|
| 6 | EE | Shigeru Oyanagi,
Kazuto Kubota,
Akihiko Nakase:
Mining WWW Access Sequence by Matrix Clustering.
WEBKDD 2002: 119-136 |
| 2001 |
|---|
| 5 | | Kazuto Kubota,
Akihiko Nakase,
Shigeru Oyanagi:
Implementation and performance evaluation of dynamic scheduling for parallel decision tree generation.
IPDPS 2001: 157 |
| 1994 |
|---|
| 4 | | Yasushi Kawakura,
Shigeru Oyanagi:
Improving the Performance of Global Communication on a 3D torus network.
ICPP (3) 1994: 193-196 |
| 1991 |
|---|
| 3 | | Noboru Tanabe,
Takashi Suzuoka,
Sadao Nakamura,
Yasushi Kawakura,
Shigeru Oyanagi:
Base-m n-cube: High Performance Interconnection Networks for Highly Parallel Computer PRODIGY.
ICPP (1) 1991: 509-516 |
| 1980 |
|---|
| 2 | | Hiroshi Hagiwara,
Shinji Tomita,
Shigeru Oyanagi,
Kiyoshi Shibayama:
A Dynamically Microprogammable Computer with Low-Level Parallelism.
IEEE Trans. Computers 29(7): 577-595 (1980) |
| 1977 |
|---|
| 1 | | Shinji Tomita,
Kiyoshi Shibayama,
Shigeru Oyanagi,
Hiroshi Hagiwara:
Hardware Organization of a Low Level Parallel Processor.
IFIP Congress 1977: 855-860 |
