2008 | ||
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3 | EE | Yuk Hei Chan, Wai Shing Fung, Lap Chi Lau, Chun Kong Yung: Degree Bounded Network Design with Metric Costs. FOCS 2008: 125-134 |
2 | EE | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong: FPGA interconnect design using logical effort. FPGA 2008: 257 |
1 | EE | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong: FPGA interconnect design using logical effort. FPL 2008: 447-450 |
1 | Wai Shing Fung | [3] |
2 | Lap Chi Lau | [3] |
3 | Philip Heng Wai Leong | [1] [2] |
4 | Haile Yu | [1] [2] |
5 | Chun Kong Yung | [3] |