| 2009 |
|---|
| 8 | EE | Andrew Putnam,
Susan J. Eggers,
Dave Bennett,
Eric Dellinger,
Jeff Mason,
Henry Styles,
Prasanna Sundararajan,
Ralph Wittig:
Performance and power of cache-based reconfigurable computing.
FPGA 2009: 281 |
| 2008 |
|---|
| 7 | EE | Andrew Putnam,
Dave Bennett,
Eric Dellinger,
Jeff Mason,
Prasanna Sundararajan:
CHiMPS: a high-level compilation flow for hybrid CPU-FPGA architectures.
FPGA 2008: 261 |
| 6 | EE | Andrew Putnam,
Dave Bennett,
Eric Dellinger,
Jeff Mason,
Prasanna Sundararajan,
Susan J. Eggers:
CHiMPS: A C-level compilation flow for hybrid CPU-FPGA architectures.
FPL 2008: 173-178 |
| 2007 |
|---|
| 5 | EE | Steven Swanson,
Andrew Schwerin,
Martha Mercaldi,
Andrew Petersen,
Andrew Putnam,
Ken Michelson,
Mark Oskin,
Susan J. Eggers:
The WaveScalar architecture.
ACM Trans. Comput. Syst. 25(2): (2007) |
| 2006 |
|---|
| 4 | EE | Martha Mercaldi,
Steven Swanson,
Andrew Petersen,
Andrew Putnam,
Andrew Schwerin,
Mark Oskin,
Susan J. Eggers:
Instruction scheduling for a tiled dataflow architecture.
ASPLOS 2006: 141-150 |
| 3 | EE | Steven Swanson,
Andrew Putnam,
Martha Mercaldi,
Martha Mercaldi,
Ken Michelson,
Andrew Petersen,
Andrew Schwerin,
Mark Oskin,
Susan J. Eggers:
Area-Performance Trade-offs in Tiled Dataflow Architectures.
ISCA 2006: 314-326 |
| 2 | EE | Andrew Petersen,
Andrew Putnam,
Martha Mercaldi,
Andrew Schwerin,
Susan J. Eggers,
Steven Swanson,
Mark Oskin:
Reducing control overhead in dataflow architectures.
PACT 2006: 182-191 |
| 1 | EE | Martha Mercaldi,
Steven Swanson,
Andrew Petersen,
Andrew Putnam,
Andrew Schwerin,
Mark Oskin,
Susan J. Eggers:
Modeling instruction placement on a spatial architecture.
SPAA 2006: 158-169 |
