| 2008 |
|---|
| 6 | EE | Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano,
Daihan Wang:
Run-time power gating of on-chip routers using look-ahead routing.
ASP-DAC 2008: 55-60 |
| 5 | EE | Daihan Wang,
Hiroki Matsutani,
Hideharu Amano,
Michihiro Koibuchi:
A link removal methodology for Networks-on-Chip on reconfigurable systems.
FPL 2008: 269-274 |
| 4 | EE | Hiroki Matsutani,
Michihiro Koibuchi,
Daihan Wang,
Hideharu Amano:
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks.
NOCS 2008: 23-32 |
| 2007 |
|---|
| 3 | EE | Daihan Wang,
Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems.
FPL 2007: 383-388 |
| 2 | EE | Daihan Wang,
Hiroki Matsutani,
Michihiro Koibuchi,
Hideharu Amano:
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs.
IEICE Transactions 90-D(12): 1914-1922 (2007) |
| 2006 |
|---|
| 1 | | Daihan Wang,
Hiroki Matsutani,
Masato Yoshimi,
Michihiro Koibuchi,
Hideharu Amano:
A Parametric Study of Scalable Interconnects on FPGAs.
ERSA 2006: 130-135 |
