| 2006 |
|---|
| 6 | EE | Subash G. Chandar,
Mahesh Mehendale,
R. Govindarajan:
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding.
VLSI Signal Processing 44(3): 245-267 (2006) |
| 2005 |
|---|
| 5 | EE | Soujanna Sarkar,
Subash G. Chandar:
An Effective Framework for Enabling the Reuse of External Soft IP.
DSD 2005: 108-113 |
| 2004 |
|---|
| 4 | EE | Subrangshu Das,
Subash G. Chandar,
Ashutosh Tiwari:
Reset Careabouts in a SoC Design.
VLSI Design 2004: 788- |
| 2001 |
|---|
| 3 | EE | Subash G. Chandar,
Mahesh Mehendale,
R. Govindarajan:
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding.
ICCAD 2001: 631-634 |
| 2000 |
|---|
| 2 | EE | Karthikeyan Madathil,
Jagdish C. Rao,
Subash G. Chandar,
Amitabh Menon,
Avinash K. Gautam,
Amit M. Brahme,
H. Udayakumar:
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores.
VLSI Design 2000: 468- |
| 1999 |
|---|
| 1 | EE | Avinash K. Gautam,
Jagdish C. Rao,
Karthikeyan Madathil,
Vilesh Shah,
H. Udayakumar,
Amitabh Menon,
Subash G. Chandar:
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology.
ICCD 1999: 340-347 |
