| 2008 |
|---|
| 6 | EE | Huaizhi Wu,
Martin D. F. Wong,
Wilsin Gosti:
Postplacement voltage assignment under performance constraints.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 2001 |
|---|
| 5 | EE | Wilsin Gosti,
Sunil P. Khatri,
Alberto L. Sangiovanni-Vincentelli:
Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement.
ICCAD 2001: 224-231 |
| 1998 |
|---|
| 4 | EE | Wilsin Gosti,
Alberto L. Sangiovanni-Vincentelli,
Tiziano Villa,
Alexander Saldanha:
An Exact Input Encoding Algorithm for BDDs Representing FSMs.
Great Lakes Symposium on VLSI 1998: 294-300 |
| 3 | EE | Wilsin Gosti,
Amit Narayan,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Wireplanning in logic synthesis.
ICCAD 1998: 26-33 |
| 1997 |
|---|
| 2 | EE | Yuji Kukimoto,
Wilsin Gosti,
Alexander Saldanha,
Robert K. Brayton:
Approximate timing analysis of combinational circuits under the XBD0 model.
ICCAD 1997: 176-181 |
| 1 | | Rajeev K. Ranjan,
Wilsin Gosti,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions.
ICCD 1997: 344-351 |
