Wilsin Gosti

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6EEHuaizhi Wu, Martin D. F. Wong, Wilsin Gosti: Postplacement voltage assignment under performance constraints. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
5EEWilsin Gosti, Sunil P. Khatri, Alberto L. Sangiovanni-Vincentelli: Addressing the Timing Closure Problem by Integrating Logic Optimization and Placement. ICCAD 2001: 224-231
4EEWilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha: An Exact Input Encoding Algorithm for BDDs Representing FSMs. Great Lakes Symposium on VLSI 1998: 294-300
3EEWilsin Gosti, Amit Narayan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Wireplanning in logic synthesis. ICCAD 1998: 26-33
2EEYuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton: Approximate timing analysis of combinational circuits under the XBD0 model. ICCAD 1997: 176-181
1 Rajeev K. Ranjan, Wilsin Gosti, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Dynamic Reordering in a Breadth-First Manipulation Based BDD Package: Challenges and Solutions. ICCD 1997: 344-351

Coauthor Index

1Robert K. Brayton [1] [2] [3]
2Sunil P. Khatri [5]
3Yuji Kukimoto [2]
4Amit Narayan [3]
5Rajeev K. Ranjan [1]
6Alexander Saldanha [2] [4]
7Alberto L. Sangiovanni-Vincentelli [1] [3] [4] [5]
8Tiziano Villa [4]
9Martin D. F. Wong (D. F. Wong) [6]
10Huaizhi Wu [6]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)