| 2006 |
|---|
| 11 | EE | Ernesto Wandeler,
Lothar Thiele,
Marcel Verhoef,
Paul Lieverse:
System architecture evaluation using modular performance analysis: a case study.
STTT 8(6): 649-667 (2006) |
| 2004 |
|---|
| 10 | | Marcel Verhoef,
Ernesto Wandeler,
Lothar Thiele,
Paul Lieverse:
System Architecture Evaluation Using Modular Performance Analysis - A Case Study.
ISoLA (Preliminary proceedings) 2004: 209-219 |
| 2002 |
|---|
| 9 | EE | Vladimir D. Zivkovic,
Paul Lieverse:
An Overview of Methodologies and Tools in the Field of System-Level Design.
Embedded Processor Design Challenges 2002: 74-88 |
| 2001 |
|---|
| 8 | EE | Paul Lieverse,
Pieter van der Wolf,
Ed F. Deprettere:
A trace transformation technique for communication refinement.
CODES 2001: 134-139 |
| 7 | EE | Paul Lieverse,
Todor Stefanov,
Pieter van der Wolf,
Ed F. Deprettere:
System Level Design with Spade: an M-JPEG Case Study.
ICCAD 2001: 31-38 |
| 6 | EE | Andy D. Pimentel,
Louis O. Hertzberger,
Paul Lieverse,
Pieter van der Wolf,
Ed F. Deprettere:
Exploring Embedded-Systems Architectures with Artemis.
IEEE Computer 34(11): 57-63 (2001) |
| 5 | EE | Paul Lieverse,
Pieter van der Wolf,
Kees A. Vissers,
Ed F. Deprettere:
A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems.
VLSI Signal Processing 29(3): 197-207 (2001) |
| 2000 |
|---|
| 4 | EE | Ed F. Deprettere,
Edwin Rijpkema,
Paul Lieverse,
Bart Kienhuis:
High Level Modeling for Parallel Executions of Nested Loop Algorithms.
ASAP 2000: 79-91 |
| 3 | EE | Erwin A. de Kock,
W. J. M. Smits,
Pieter van der Wolf,
Jean-Yves Brunel,
W. M. Kruijtzer,
Paul Lieverse,
Kees A. Vissers,
Gerben Essink:
YAPI: application modeling for signal processing systems.
DAC 2000: 402-405 |
| 1999 |
|---|
| 2 | EE | Pieter van der Wolf,
Paul Lieverse,
Mudit Goel,
David La Hei,
Kees A. Vissers:
An MPEG-2 decoder case study as a driver for a system level design methodology.
CODES 1999: 33-37 |
| 1 | EE | Paul Lieverse,
Ed F. Deprettere,
Bart Kienhuis,
Erwin A. de Kock:
A Clustering Approach to Explore Grain-Sizes in the Definition of Processing Elements in Dataflow Architectures.
VLSI Signal Processing 22(1): 9-20 (1999) |
