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José Alberto Espejo

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2003
8EEEnrique San Millán, Luis Entrena, José Alberto Espejo, Celia López: Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. Journal of Systems Architecture 49(12-15): 529-541 (2003)
2001
7EEJosé Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Functional extension of structural logic optimization techniques. ASP-DAC 2001: 467-472
6EEJosé Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Generalized reasoning scheme for redundancy addition and removal logic optimization. DATE 2001: 391-397
5EEEnrique San Millán, Luis Entrena, José Alberto Espejo: On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization. DSD 2001: 292-299
4EEEnrique San Millán, Luis Entrena, José Alberto Espejo: On the Optimization Power of Redundancy Addition and Removal Techniques for Sequential Circuits. ICCAD 2001: 91-94
3EELuis Entrena, Celia López, Emilio Olías, Enrique San Millán, José Alberto Espejo: Logic Optimization of Unidirectional Circuits with Structural Methods. IOLTW 2001: 43-47
1999
2EEEnrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno: Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization. DATE 1999: 516-520
1EEJosé Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Logic Restructuring for MUX-Based FPGAs. EUROMICRO 1999: 1161-

Coauthor Index

1Silvia Chiusano [2]
2Fulvio Corno [2]
3Luis Entrena (Luis Entrena-Arrontes) [1] [2] [3] [4] [5] [6] [7] [8]
4Celia López-Ongil (Celia López) [3] [8]
5Enrique San Millán [1] [2] [3] [4] [5] [6] [7] [8]
6Emilio Olías [1] [3] [6] [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)