| 2007 |
|---|
| 4 | EE | Matthew M. Ziegler,
Gary S. Ditlow,
Stephen V. Kosonocky,
Zhenyu Qi,
Mircea R. Stan:
Structured and tuned array generation (STAG) for high-performance random logic.
ACM Great Lakes Symposium on VLSI 2007: 257-262 |
| 1999 |
|---|
| 3 | | Gary S. Ditlow,
Anshul Gupta,
Richard Moore,
David Moran,
Ralph Williams,
Tom Wilkins:
Parallel Analysis of IC Power Distribution Networks.
PPSC 1999 |
| 1992 |
|---|
| 2 | EE | D. A. Zein,
O. P. Engel,
Gary S. Ditlow:
HLSIM - A New Hierarchical Logic Simulator and Netlist Converter.
DAC 1992: 432-437 |
| 1984 |
|---|
| 1 | | Jacob Savir,
Gary S. Ditlow,
Paul H. Bardell:
Random Pattern Testability.
IEEE Trans. Computers 33(1): 79-90 (1984) |
