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A. Stoll

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1992
2EEA. Stoll, Peter Duzy: High-Level Synthesis from VHDL with Exact Timing Constraints. DAC 1992: 188-193
1 J. Biesenack, Norbert Wehn, A. Stoll, Michael Payer: Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits 1992: 263-274

Coauthor Index

1J. Biesenack [1]
2Peter Duzy [2]
3Michael Payer [1]
4Norbert Wehn [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)