2007 |
10 | EE | Jun-Fu Huang,
Victor C. Y. Chang,
Sally Liu,
Kelvin Y. Y. Doong,
Keh-Jeng Chang:
Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFM.
ASP-DAC 2007: 221-225 |
2005 |
9 | EE | Chung-Kuan Cheng,
Steve Lin,
Andrew B. Kahng,
Keh-Jeng Chang,
Vijay Pitchumani,
Toshiyuki Shibuya,
Roberto Suaya,
Zhiping Yu,
Fook-Luen Heng,
Don MacMillen:
Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?
ASP-DAC 2005 |
2004 |
8 | EE | Keh-Jeng Chang:
Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability.
IWSOC 2004: 219-222 |
2000 |
7 | EE | Li-Fu Chang,
Keh-Jeng Chang,
Robert Mathews:
Simulating frequency-dependent current distribution for inductance modeling of on-chip copper interconnects.
ISPD 2000: 117-120 |
6 | EE | Li-Fu Chang,
Keh-Jeng Chang,
Christophe J. Bianchi:
A Proposal for Accurately Modeling Frequency-Dependent On-Chip Interconnect Impedance.
ISQED 2000: 375-378 |
1999 |
5 | | Martin G. Walker,
Keh-Jeng Chang,
Christophe J. Bianchi:
SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters?
VLSI 1999: 649-658 |
4 | | Li-Fu Chang,
Abhay Dubey,
Keh-Jeng Chang,
Robert Mathews,
Ken Wong:
Incorporating Process Induced Effects into RC Extraction.
VLSI Design 1999: 12-17 |
1992 |
3 | EE | Norman H. Chang,
Keh-Jeng Chang,
John Leo,
Ken Lee,
Soo-Young Oh:
IPDA: Interconnect Performance Design Assistant.
DAC 1992: 472-477 |
2 | | Soo-Young Oh,
Keh-Jeng Chang,
Norman Chang,
Ken Lee:
Interconnect Modeling and Design in High-Speed VLSI/ULSI Systems.
ICCD 1992: 184-189 |
1991 |
1 | | Keh-Jeng Chang,
Soo-Young Oh,
Ken Lee:
HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs.
ICCAD 1991: 294-297 |