2002 |
19 | EE | Laurence Goodby,
Alex Orailoglu,
Paul M. Chau:
Microarchitectural synthesis of performance-constrained, low-power VLSI designs.
ACM Trans. Design Autom. Electr. Syst. 7(1): 122-136 (2002) |
2000 |
18 | | Philip P. Dang,
Paul M. Chau:
Image encryption for multimedia applications.
Computers and Their Applications 2000: 203-206 |
1999 |
17 | | Jeremy Risher,
Philip P. Dang,
Paul M. Chau:
Reconfigurable Hardware for Encryption.
Applied Informatics 1999: 554-557 |
16 | | Philip P. Dang,
Paul M. Chau:
FPGA architecture for noise filters on a reconfigurable processor.
Computers and Their Applications 1999: 250-253 |
15 | EE | Michael B. Bendak,
Baernard A. Xavier,
Paul M. Chau:
A 1.2 GHz CMOS quadrature self-oscillating mixer.
ISCAS (5) 1999: 434-437 |
1998 |
14 | | Paul M. Chau,
Gerald Clark,
Anthony V. Sebald:
Evolvable Hardware Control for Dynamic Reconfigurable and Adaptive Computing.
Evolutionary Programming 1998: 137-146 |
13 | EE | Jeanette F. Arrigo,
Kevin J. Page,
Paul M. Chau,
N. C. Tien:
Reconfigurable Processing for Robust Navigation and Control (Abstract).
FPGA 1998: 260 |
12 | | Philip P. Dang,
Paul M. Chau:
A Feature Extraction Application on a Reconfigurable Image Processor.
IVCNZ 1998: 352-356 |
1996 |
11 | EE | Takeo Hamada,
Chung-Kuan Cheng,
Paul M. Chau:
A wire length estimation technique utilizing neighborhood density equations.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 912-922 (1996) |
10 | EE | Dan Picker,
Ronald D. Fellman,
Paul M. Chau:
An extension to the SCI flow control protocol for increased network efficiency.
IEEE/ACM Trans. Netw. 4(1): 71-85 (1996) |
1995 |
9 | EE | Sati Banerjee,
Paul M. Chau,
Ronald D. Fellman:
Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems.
VLSI Signal Processing 11(1-2): 21-34 (1995) |
1994 |
8 | EE | P. H. Kelly,
Kevin J. Page,
Paul M. Chau:
Rapid Prototyping of ASIC Based Systems.
DAC 1994: 460-465 |
7 | | Laurence Goodby,
Alex Orailoglu,
Paul M. Chau:
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs.
ICCD 1994: 323-326 |
1993 |
6 | EE | Takeo Hamada,
Chung-Kuan Cheng,
Paul M. Chau:
Prime: A Timing-Driven Placement Tool using A Piecewise Linear Resistive Network Approach.
DAC 1993: 531-536 |
5 | EE | Steven S. Watkins,
Paul M. Chau,
Raoul Tawel,
Bjorn Lambrigtsen,
Mark Plutowski:
A Hybrid Radial Basis Function Neurocomputer and Its Applications.
NIPS 1993: 850-857 |
4 | EE | Yu-jhih Wu,
Michael D. Alston,
Paul M. Chau:
Dynamic adaptation of quantization thresholds for soft-decision viterbi decoding with a reinforcement learning neural network.
VLSI Signal Processing 6(1): 77-84 (1993) |
1992 |
3 | EE | Takeo Hamada,
Chung-Kuan Cheng,
Paul M. Chau:
A Wire Length Estimation Technique Utilizing Neighborhood Density Equations.
DAC 1992: 57-61 |
2 | EE | Paul M. Chau,
Scott R. Powell:
Power dissipation of VLSI array processing systems.
VLSI Signal Processing 4(2-3): 199-212 (1992) |
1991 |
1 | EE | Amir K. Hekmatpour,
Alex Orailoglu,
Paul M. Chau:
Hierarchical Modeling of the VLSI Design Process.
IEEE Expert 6(2): 56-70 (1991) |