Peter Duzy

1994
3	EE	Norbert Wehn, J. Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, S. Rumler: Scheduling of behavioral VHDL by retiming techniques. EURO-DAC 1994: 546-551
1993
2	EE	J. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, Michael Payer, Michael Pilsl, S. Rumler, H. Soukup, Norbert Wehn, Peter Duzy: The Siemens high-level synthesis system CALLAS. IEEE Trans. VLSI Syst. 1(3): 244-253 (1993)
1992
1	EE	A. Stoll, Peter Duzy: High-Level Synthesis from VHDL with Exact Timing Constraints. DAC 1992: 188-193

Coauthor Index

1	J. Biesenack	[2] [3]
2	M. Koster	[2]
3	A. Langmaier	[2]
4	T. Langmaier	[3]
5	S. Ledeux	[2]
6	S. Marz	[2]
7	Michael Münch	[3]
8	Michael Payer	[2]
9	Michael Pilsl	[2] [3]
10	S. Rumler	[2] [3]
11	H. Soukup	[2]
12	A. Stoll	[1]
13	Norbert Wehn	[2] [3]