17. FPL 2007:
Amsterdam,
The Netherlands
Koen Bertels, Walid A. Najjar, Arjan J. van Genderen, Stamatis Vassiliadis (Eds.):
FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007.
IEEE 2007, ISBN 1-4244-1060-6 BibTeX
Keynotes
Applications I
Design Tools & Compilers I
Multicore Systems
Applications II
- Ludovico de Souza, John D. Bunton, Duncan Campbell-Wilson, Roger J. Cappallo, Bart Kincaid:
A Radio Astronomy Correlator Optimized for the XILINX VIRTEX-4 SX FPGA.
62-67
Electronic Edition (link) BibTeX
- Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijay Narayanan, K. Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun:
TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.
68-73
Electronic Edition (link) BibTeX
- S. Murtaza, Alfons G. Hoekstra, Peter M. A. Sloot:
Performance Modeling of 2D Cellular Automata on FPGA.
74-78
Electronic Edition (link) BibTeX
High Performance Computing
Run-Time Support I
- Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David L. Andrews:
Supporting High Level Language Semantics Within Hardware Resident Threads.
98-103
Electronic Edition (link) BibTeX
- Aric D. Blumer, Henning S. Mortveit, Cameron D. Patterson:
Formal Modeling of Process Migration.
104-110
Electronic Edition (link) BibTeX
- John Shield, Peter Sutton, Philip Machanick:
Dynamic Cache Switching in Reconfigurable Embedded Systems.
111-116
Electronic Edition (link) BibTeX
Placement & Routing I
Biology Applications I
Power I
Communication & Security
- Graham Schelle, Jeff Fifield, Dirk Grunwald:
A Software Defined Radio Application Utilizing Modern FPGAs and NoC Interconnects.
177-182
Electronic Edition (link) BibTeX
- Encarnación Castillo, Luis Parrilla, Antonio García, Uwe Meyer-Bäse, Antonio Lloris-Ruíz:
Intellectual Property Protection of HDL IP Cores Through Automated Sognature Hosting.
183-188
Electronic Edition (link) BibTeX
- Jorge Guajardo, Sandeep Kumar, Geert Jan Schrijen, Pim Tuyls:
Physical Unclonable Functions, FPGAs and Public-Key Crypto for IP Protection.
189-195
Electronic Edition (link) BibTeX
Architecture I
Image & Video Processing
Power II
Biology Applications II
- Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Yasunori Osana, Akira Funahashi, Noriko Hiroi, Yuichiro Shibata, Naoki Iwanaga, Hideki Yamada, Hiroaki Kitano, Hideharu Amano:
FPGA Implementation of a Data-Driven Stochastic Biochemical Simulator with the Next Reaction Method.
254-259
Electronic Edition (link) BibTeX
- Octavian Cret, Zsolt Mathe, Paul Ciobanu, Sonia Marginean, Cristian Lelutiu:
GENDIV - A Hardware Algorithm for Intron and Exon String Detection in DNA Chains.
260-266
Electronic Edition (link) BibTeX
- Kevin M. Irick, Michael DeBole, Vijaykrishnan Narayanan, Rajeev Sharma, Hankyu Moon, Satish Mummareddy:
A Unified Streaming Architecture for Real Time Face Detection and Gender Classification.
267-272
Electronic Edition (link) BibTeX
Design Tools & Compilers II
Placement & Routing II
Architecture II
Design Tools & Compilers III
Placement & Routing III
Networks on Chip
EU Session
- Andreas Herrholz, Frank Oppenheimer, Philipp A. Hartmann, Andreas Schallenberg, Wolfgang Nebel, Christoph Grimm, Markus Damm, Jan Haase, F. Brame, Fernando Herrera, Eugenio Villar, Ingo Sander, Axel Jantsch, Anne-Marie Fouilliart, M. Martinez:
The ANDRES Project: Analysis and Design of Run-Time Reconfigurable, Heterogeneous Systems.
396-401
Electronic Edition (link) BibTeX
- Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte, Georgi Gaydadjiev, Yana Yankova, Vlad Mihai Sima, Kamana Sigdel, Roel Meeuws, Stamatis Vassiliadis:
HARTES Toolchain Early Evaluation: Profiling, Compilation and HDL Generation.
402-408
Electronic Edition (link) BibTeX
- Florian Thoma, Matthias Kühnle, Philippe Bonnot, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker:
MORPHEUS: Heterogeneous Reconfigurable Computing.
409-414
Electronic Edition (link) BibTeX
- Katarina Paulsson, Michael Hübner, Jürgen Becker, Jean-Marc Philippe, Christian Gamrat:
On-line Routing of Reconfigurable Functions for Future Self-Adaptive Systems - Investigations within the ÆTHER Project.
415-422
Electronic Edition (link) BibTeX
Design Tools & Compilers IV
Run-Time Support II
Poster Session 1
- José L. Núñez-Yáñez, Vassilios A. Chouliaras, Jiri Gaisler:
Dynamic Voltage Scaling in a FPGA-based System-on-Chip.
459-462
Electronic Edition (link) BibTeX
- Martijn T. Bennebroek, Alexander Danilin:
Multiplexer-based routing fabric for reconfigurable logic.
463-466
Electronic Edition (link) BibTeX
- Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker:
H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture.
467-471
Electronic Edition (link) BibTeX
- Roberto Gutierrez, Javier Valls:
Implementation on FPGA of a LUT-based atan(Y/X) operator suitable for Synchronization Algorithms.
472-475
Electronic Edition (link) BibTeX
- Andrew Morton, Jeffrey Liu, Insop Song:
Efficient Priority-Queue Data Structure for Hardware Implementation.
476-479
Electronic Edition (link) BibTeX
- Ralf Laue, Oliver Kelm, Sebastian Schipp, Abdulhadi Shoufan, Sorin A. Huss:
Compact AES-based Architecture for Symmetric Encryption, Hash Function, and Random Number Generation.
480-484
Electronic Edition (link) BibTeX
- Mariano Fons, Francisco Fons, Enrique Cantó, Mariano López:
Design of a hardware accelerator for fingerprint alignment.
485-488
Electronic Edition (link) BibTeX
- Shingo Masuno, Tsutomu Maruyama, Yoshiki Yamaguchi, Akihiko Konagaya:
An FPGA Implementation of Multiple Sequence Alignment Based on Carrillo-Lipman Method.
489-492
Electronic Edition (link) BibTeX
- Kenji Kanazawa, Tsutomu Maruyama:
An FPGA Solver for Very Large SAT Problems.
493-496
Electronic Edition (link) BibTeX
- Ioannis Nousias, Sami Khawam, Mark Milward, Mark Muir, Tughrul Arslan:
A Multi Objective GA based Physical Placement Algorithm for Heterogeneous Dynamically Reconfigurable Arrays.
497-500
Electronic Edition (link) BibTeX
Poster Session 2
- Ricardo Menotti, Eduardo Marques, João M. P. Cardoso:
Aggressive Loop Pipelining for Reconfigurable Architectures.
501-502
Electronic Edition (link) BibTeX
- Hagen Gädke, Andreas Koch:
Comrade - A Compiler for Adaptive Computing Systems Using a Novel Fast Speculation Technique.
503-504
Electronic Edition (link) BibTeX
- Thomas Panhofer, Martin Delvai:
Self-Healing Circuits for Space-Applications.
505-506
Electronic Edition (link) BibTeX
- Proshanta Saha:
Automatic Software Hardware Co-Design for Reconfigurable Computing Systems.
507-508
Electronic Edition (link) BibTeX
- Chi Wai Yu:
VPH - A Tool for Exploring Hybrid FPGAs.
509-510
Electronic Edition (link) BibTeX
- Jim Stevens:
Hybridthreads Compiler: Generation of Application Specific Hardware Thread Cores from C.
511-512
Electronic Edition (link) BibTeX
- Peter M. Athanas, J. Bowen, T. Dunham, Cameron Patterson, J. Rice, Matthew Shelburne, J. Surís, Mark B. Bucciero, Jonathan Graf:
Wires On Demand: Run-Time Communication Synthesis for Reconfigurable Computing.
513-516
Electronic Edition (link) BibTeX
- Ashutosh Pal, M. Balakrishnan:
A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures.
517-520
Electronic Edition (link) BibTeX
- Micha Nelissen, Kees van Berkel, Sergei Sawitzki:
Mapping A VLIWxSIMD Processor on an FPGA: Scalability and Performance.
521-524
Electronic Edition (link) BibTeX
- Alberto Gallini, Lorenzo Pavesi, Claudio Ferretti, Alberto Rosti, Sara Bocchio:
An Automatic Compilation Framework for Configurable Architectures.
525-528
Electronic Edition (link) BibTeX
- Vinay Sriram, David Kearney:
A high throughput area time efficient pseudo uniform random number generator based on the TT800 algorithm.
529-532
Electronic Edition (link) BibTeX
- Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid:
Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System.
533-536
Electronic Edition (link) BibTeX
Poster Session 3
- Stamatis Vassiliadis, Filipa Duarte, Stephan Wong:
A Load/Store Unit for a Memcpy Hardware Accelerator.
537-541
Electronic Edition (link) BibTeX
- Jan Torben Weinkopf, Klaus Harbich, Erich Barke:
Incremental Fault Emulation.
542-545
Electronic Edition (link) BibTeX
- Graeme Stewart, David Renshaw, Martyn Riley:
A novel motion estimation power reduction technique.
546-549
Electronic Edition (link) BibTeX
- Motoki Amagasaki, Ryoichi Yamaguchi, Kazunori Matsuyama, Masahiro Iida, Toshinori Sueyoshi:
A Variable Grain Logic Cell Architecture for Reconfigurable Logic Cores.
550-553
Electronic Edition (link) BibTeX
- Takamasa Kanamori, Hideharu Amano, Masatoshi Arai, Daisuke Konno, Tomomichi Nanba, Yoshiaki Ajioka:
A High Speed License Plate Recognition System on an FPGA.
554-557
Electronic Edition (link) BibTeX
- A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
REDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.
558-561
Electronic Edition (link) BibTeX
- Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink, Pascal T. Wolkotte, Gerard J. M. Smit:
Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core.
562-566
Electronic Edition (link) BibTeX
- José M. Claver, P. Agustí, G. León, Manel Canseco:
A Reprogrammable and Scalable Multimedia Traffic Generator/Monitor on FPGA.
567-570
Electronic Edition (link) BibTeX
- Rob Beun, Irek Karkowski, Maarten Ditzel:
C++ based design flow for reconfigurable image processing systems.
571-575
Electronic Edition (link) BibTeX
- Vanderlei Bonato, Eduardo Marques, George A. Constantinides:
A floating-point Extended Kalman Filter implementation for autonomous mobile robots.
576-579
Electronic Edition (link) BibTeX
- Hristo Nikolov, Todor Stefanov, Ed F. Deprettere:
Efficient External Memory Interface for Multi-processor Platforms Realized on FPGA Chips.
580-584
Electronic Edition (link) BibTeX
- Aric D. Blumer, Cameron D. Patterson:
Hardware/Software Process Migration and RTL Simulation.
585-588
Electronic Edition (link) BibTeX
- Sayaka Shida, Yuichiro Shibata, Kiyoshi Oguri, Duncan A. Buell:
Implementation of a barotropic operator for ocean model simulation using a reconfigurable machine.
589-592
Electronic Edition (link) BibTeX
Poster Session 4
- Kester Clegg, Susan Stepney, Tim Clarke:
Evolutionary Search Applied to Reconfigurable Analogue Control.
593-596
Electronic Edition (link) BibTeX
- Gaye Lightbody, Roger Woods, Jonathan Francey:
Soft IP core implementation of recursive least squares filter using only multplicative and additive operators.
597-600
Electronic Edition (link) BibTeX
- Andrew G. Schmidt, Ron Sass:
Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores.
601-604
Electronic Edition (link) BibTeX
- Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser:
A Design Flow to Map Parallel Applications onto FPGAs.
605-608
Electronic Edition (link) BibTeX
- Irfan Syed, John A. Williams, Neil W. Bergmann:
A Hybrid Reconfigurable Cluster-on-Chip Architecture With Message Passing Interface For Image Processing Applications.
609-612
Electronic Edition (link) BibTeX
- Love Singhal, Elaheh Bozorgzadeh:
Novel Multi-Layer floorplanning for Heterogeneous FPGAs.
613-616
Electronic Edition (link) BibTeX
- William G. Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer:
Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems.
617-620
Electronic Edition (link) BibTeX
- Jiri Kadlec, Roman Bartosinski, Martin Danek:
Accelerating Microblaze Floating Point Operations.
621-624
Electronic Edition (link) BibTeX
- John Shield, Peter Sutton, Philip Machanick:
Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration.
625-628
Electronic Edition (link) BibTeX
- José M. Claver, G. León:
High Level Power Optimization by Type Inference on the Generation of Application Specific Circuits on FPGAs.
629-632
Electronic Edition (link) BibTeX
- Sven-Ole Voigt, Thomas Teufel:
Dynamically reconfigurable dataflow architecture for high-performance digital signal processing on multi-FPGA platforms.
633-637
Electronic Edition (link) BibTeX
- Eduardo Mesquita, Helen Franck, Luciano Volcan Agostini, José Luís Güntzel:
RIC Fast Adder and its Set Tolerant Implementation in FPGAs.
638-641
Electronic Edition (link) BibTeX
Poster Session 5
- Guerric Meurice de Dormale, John Bass, Jean-Jacques Quisquater:
Solving RC5 Challenges with Hardware -- a Distributed.net Perspective --.
642-647
Electronic Edition (link) BibTeX
- Tomas Dedek, Tomas Marek, Tomás Martínek:
High Level Abstraction Language as an Alternative to Embedded Processors for Internet Packet Processing in FPGA.
648-651
Electronic Edition (link) BibTeX
- Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris:
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support.
652-655
Electronic Edition (link) BibTeX
- Pavel Zemcík, Martin Zádník:
AdaBoost Engine.
656-660
Electronic Edition (link) BibTeX
- Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic:
An FPGA Based Memory Efficient Shared Buffer Implementation.
661-664
Electronic Edition (link) BibTeX
- Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley:
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.
665-669
Electronic Edition (link) BibTeX
- Tamer Güdü:
A New Scalable Hardware Architecture for RSA Algorithm.
670-674
Electronic Edition (link) BibTeX
- Irwin O. Kennedy:
Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive.
675-678
Electronic Edition (link) BibTeX
- Stefan Raaijmakers, Stephan Wong:
Run-time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II-Pro.
679-683
Electronic Edition (link) BibTeX
- Julio Dondo, Fernando Rincón, Jesús Barba, Francisco Moya, Felix Jesús Villanueva, David Villa, Juan Carlos López:
Dynamic reconfiguration management based on a distributed object model.
684-687
Electronic Edition (link) BibTeX
- Lars Braun, Michael Hübner, Jürgen Becker, Thomas Perschke, Volker Schatz, Stefan Bach:
Circuit Switched Run-Time Adaptive Network-on-Chip for Image Processing Applications.
688-691
Electronic Edition (link) BibTeX
- Bas Breijer, Filipa Duarte, Stephan Wong:
An OCM based shared Memory controller for Virtex 4.
692-696
Electronic Edition (link) BibTeX
- Yana Yankova, Koen Bertels, Georgi Kuzmanov, Georgi Gaydadjiev, Yi Lu, Stamatis Vassiliadis:
DWARV: DelftWorkBench Automated Reconfigurable VHDL Generator.
697-701
Electronic Edition (link) BibTeX
- Antonio Jimeno-Morenilla, Antonio Martínez, Sergio Cuenca, Jose Luis Sánchez-Romero:
Accelerating tool path computing in CAD/CAM: A FPGA architecture for turning lathe machining..
702-705
Electronic Edition (link) BibTeX
Poster Session 6
- Diego P. Morales, Antonio García, Alberto J. Palma, Antonio Martínez-Olmos, Encarnación Castillo:
Exploiting Analog and Digital Reconfiguration for Smart Sensor Interfacing.
706-709
Electronic Edition (link) BibTeX
- Harding Djakou Chati, Felix Mühlbauer, Tim Braun, Christophe Bobda, Karsten Berns:
SoPC architecture for a Key Point Detector.
710-713
Electronic Edition (link) BibTeX
- Dang Ba Khac Trieu, Tsutomu Maruyama:
A Pipeline Implementation of a Watershed Algorithm on FPGA.
714-717
Electronic Edition (link) BibTeX
- Ernest Jamro, Kazimierz Wiatr, Maciej Wielgosz:
FPGA Implementation of 64-bit Exponential Function for HPC.
718-721
Electronic Edition (link) BibTeX
- Philipp Graf, Michael Hübner, Klaus D. Müller-Glaser, Jürgen Becker:
A Graphical Model-Level Debugger for Heterogenous Reconfigurable Architectures.
722-725
Electronic Edition (link) BibTeX
- Miguel Ribeiro, Leonel Sousa:
A Run-time Reconfigurable Processor for Video Motion Estimation.
726-729
Electronic Edition (link) BibTeX
- Yvan Eustache, Jean-Philippe Diguet:
Confiuartion Management in the Context of Self Adapative Systems.
730-734
Electronic Edition (link) BibTeX
- Roel Meeuws, Yana Yankova, Koen Bertels, Georgi Gaydadjiev, Stamatis Vassiliadis:
A Quantitative Prediction Model for Hardware/Software Partitioning.
735-739
Electronic Edition (link) BibTeX
- Florian Dittmann, Stefan Frank:
Caching in Real-time Reconfiguration Port Scheduling.
740-744
Electronic Edition (link) BibTeX
- Kristopher D. Peterson, Justin L. Tripp:
Effective Automatic Memory Allocation Algorithm Based on Schedule Length in Cycles in a Novel C to FPGA Compiler.
745-748
Electronic Edition (link) BibTeX
- Audip Pandit, Ali Akoglu:
Wirelength Prediction for FPGAs.
749-752
Electronic Edition (link) BibTeX
- Slavisa Jovanovic, Camel Tanougast, Christophe Bobda, Serge Weber:
CuNoC: A Scalable Dynamic NoC for Dynamically Reconfigurable FPGAs.
753-756
Electronic Edition (link) BibTeX
Poster Session 7
- Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan:
System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems.
757-760
Electronic Edition (link) BibTeX
- Gerald Hempel, Christian Hochberger:
A resource optimized SoC Kit for FPGAs.
761-764
Electronic Edition (link) BibTeX
- Brandon Harris, Arpith C. Jacob, Joseph M. Lancaster, Jeremy Buhler, Roger D. Chamberlain:
A Banded Smith-Waterman FPGA Accelerator for Mercury BLASTP.
765-769
Electronic Edition (link) BibTeX
- F. Javier Toledo-Moreo, A. Legaz-Cano, J. Javier Martínez-Álvarez, Juan Martínez-Alajarín, Ramón Ruiz Merino:
Compression system for the phonocardiographic signal.
770-773
Electronic Edition (link) BibTeX
- Zdenek Pohl, Milan Tichý:
RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator for the Microblaze Processor.
774-777
Electronic Edition (link) BibTeX
- Angelo Kuti Lusala, Philippe Manet, Bertrand Rousseau, Jean-Didier Legat:
NoC Implementation in FPGA Using Torus Topology.
778-781
Electronic Edition (link) BibTeX
- Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir:
Microarchitectural Enhancements for Configurable Multi-Threaded Soft Processors.
782-785
Electronic Edition (link) BibTeX
- David Gregg, Colm McSweeney, Ciarán McElroy, Fergal Connor, Séamas McGettrick, David Moloney, Dermot Geraghty:
FPGA based Sparse Matrix Vector Multiplication using Commodity DRAM Memory.
786-791
Electronic Edition (link) BibTeX
- Karthick Parashar, Nitin Chandrachoodan:
A Novel Event Based Simulation Algorithm for Sequential Digital Circuit Simulation.
792-795
Electronic Edition (link) BibTeX
- Yohei Hasegawa, Hideharu Amano:
Design Methodology and Trade-offs Analysis for Parameterized Dynamically Reconfigurable Processor Arrays.
796-799
Electronic Edition (link) BibTeX
- Andreas Ehliar, Dake Liu:
An fpga based open source network-on-chip architecture.
800-803
Electronic Edition (link) BibTeX
- Martin Kosek, Jan Korenek:
FlowContext: Flexible Platform for Multigigabit Stateful Packet Processing.
804-807
Electronic Edition (link) BibTeX
- Hideki Yamada, Naoki Iwanaga, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yow Iwaoka, Yuri Nishikawa, Toshinori Kojima, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Hiroaki Kitano, Kiyoshi Oguri:
A Combining technique of rate law functions for a cost-effective reconfigurable biological simulator.
808-811
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:12:43 2009
by Michael Ley (ley@uni-trier.de)