| 2009 |
|---|
| 51 | EE | Petr Svenda,
Lukás Sekanina,
Václav Matyás:
Evolutionary design of secrecy amplification protocols for wireless sensor networks.
WISEC 2009: 225-236 |
| 2008 |
|---|
| 50 | | Gregory Hornby,
Lukás Sekanina,
Pauline C. Haddow:
Evolvable Systems: From Biology to Hardware, 8th International Conference, ICES 2008, Prague, Czech Republic, September 21-24, 2008. Proceedings
Springer 2008 |
| 49 | EE | Zdenek Vasícek,
Lukás Sekanina:
Novel Hardware Implementation of Adaptive Median Filters.
DDECS 2008: 110-115 |
| 48 | EE | Lukás Starecek,
Lukás Sekanina,
Zdenek Kotásek:
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration.
DDECS 2008: 255-268 |
| 47 | EE | Zdenek Vasícek,
Lukás Sekanina:
Hardware Accelerators for Cartesian Genetic Programming.
EuroGP 2008: 230-241 |
| 46 | EE | Lukás Sekanina,
Petr Mikusek:
Analysis of Reconfigurable Logic Blocks for Evolvable Digital Architectures.
EvoWorkshops 2008: 144-153 |
| 45 | EE | Zdenek Vasícek,
Martin Zádník,
Lukás Sekanina,
Jirí Tobola:
On Evolutionary Synthesis of Linear Transforms in FPGA.
ICES 2008: 141-152 |
| 44 | EE | Ludek Zaloudek,
Lukás Sekanina:
Transistor-Level Evolution of Digital Circuits Using a Special Circuit Simulator.
ICES 2008: 320-331 |
| 43 | EE | Mircea Gh. Negoita,
Lukás Sekanina,
Adrian Stoica:
Adaptive and Evolvable Hardware and Systems: The State of the Art and the Prospectus for Future Development.
KES (3) 2008: 310-318 |
| 42 | EE | Tomas Pecenka,
Lukás Sekanina,
Zdenek Kotásek:
Evolution of synthetic RTL benchmark circuits with predefined testability.
ACM Trans. Design Autom. Electr. Syst. 13(3): (2008) |
| 2007 |
|---|
| 41 | EE | Zdenek Vasícek,
Lukás Sekanina:
Evaluation of a New Platform For Image Filter Evolution.
AHS 2007: 577-586 |
| 40 | | Lukás Sekanina:
Design and Analysis of a New Self-Testing Adder which Utilizes Polymorphic Gates.
DDECS 2007: 243-246 |
| 39 | EE | Karel Slaný,
Lukás Sekanina:
Fitness Landscape Analysis and Image Filter Evolution Using Functional-Level CGP.
EuroGP 2007: 311-320 |
| 38 | EE | Zdenek Vasícek,
Lukás Sekanina:
An area-efficient alternative to adaptive median filtering in FPGAs.
FPL 2007: 216-221 |
| 37 | EE | Zbysek Gajda,
Lukás Sekanina:
Reducing the number of transistors in digital circuits using gate-level evolutionary design.
GECCO 2007: 245-252 |
| 36 | EE | Lukás Sekanina:
Evolvable hardware.
GECCO (Companion) 2007: 3627-3644 |
| 35 | EE | Lukás Sekanina:
Evolution of Polymorphic Self-checking Circuits.
ICES 2007: 186-197 |
| 34 | EE | Zdenek Vasícek,
Lukás Sekanina:
Reducing the Area on a Chip Using a Bank of Evolved Filters.
ICES 2007: 222-232 |
| 33 | EE | Lukás Sekanina:
Evolutionary functional recovery in virtual reconfigurable circuits.
JETC 3(2): (2007) |
| 2006 |
|---|
| 32 | EE | Lukás Sekanina:
Evolutionary Design of Digital Circuits: Where Are Current Limits?
AHS 2006: 171-178 |
| 31 | EE | Lukás Sekanina,
Lukás Starecek,
Zbysek Gajda,
Zdenek Kotásek:
Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage.
AHS 2006: 186-193 |
| 30 | | Richard Ruzicka,
Lukás Sekanina:
Evolutionary circuit design in REPOMO - reconfigurable polymorphic module.
Computational Intelligence 2006: 239-244 |
| 29 | EE | Lukás Sekanina:
On dependability of FPGA-based evolvable hardware systems that utilize virtual reconfigurable circuits.
Conf. Computing Frontiers 2006: 221-228 |
| 28 | | Tomas Pecenka,
Zdenek Kotásek,
Lukás Sekanina:
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties.
DDECS 2006: 285-289 |
| 27 | | Lukás Sekanina,
Lukás Starecek,
Zdenek Kotásek:
Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules.
DDECS 2006: 85-86 |
| 26 | EE | Tomas Pecenka,
Josef Strnadel,
Zdenek Kotásek,
Lukás Sekanina:
Testability Estimation Based on Controllability and Observability Parameters.
DSD 2006: 504-514 |
| 25 | EE | Lukás Sekanina,
Zdenek Vasícek:
On the Practical Limits of the Evolutionary Digital Filter Design at the Gate Level.
EvoWorkshops 2006: 344-355 |
| 2005 |
|---|
| 24 | EE | Lukás Sekanina:
Evolutionary Design of Gate-Level Polymorphic Digital Circuits.
EvoWorkshops 2005: 185-194 |
| 23 | EE | Tomas Pecenka,
Zdenek Kotásek,
Lukás Sekanina,
Josef Strnadel:
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties.
Evolvable Hardware 2005: 51-58 |
| 22 | EE | Lukás Sekanina,
Ricardo Salem Zebulum:
Evolutionary Discovering of the Concept of the Discrete State at the Transistor Level.
Evolvable Hardware 2005: 73-78 |
| 21 | EE | Michal Bidlo,
Lukás Sekanina:
Providing information from the environment for growing electronic circuits through polymorphic gates.
GECCO Workshops 2005: 242-248 |
| 20 | EE | Ricardo Salem Zebulum,
Adrian Stoica,
Didier Keymeulen,
Lukás Sekanina,
Rajeshuni Ramesham,
Xin Guo:
Evolvable Hardware System at Extreme Low Temperatures.
ICES 2005: 37-45 |
| 19 | EE | Jan Korenek,
Lukás Sekanina:
Intrinsic Evolution of Sorting Networks: A Novel Complete Hardware Implementation for FPGAs.
ICES 2005: 46-55 |
| 18 | EE | Tomás Martínek,
Lukás Sekanina:
An Evolvable Image Filter: Experimental Evaluation of a Complete Hardware Implementation in FPGA.
ICES 2005: 76-85 |
| 17 | EE | Lukás Sekanina,
Ricardo Salem Zebulum:
Intrinsic Evolution of Controllable Oscillators in FPTA-2.
ICES 2005: 98-107 |
| 16 | EE | Lukás Sekanina,
Michal Bidlo:
Evolutionary Design of Arbitrarily Large Sorting Networks Using Development.
Genetic Programming and Evolvable Machines 6(3): 319-347 (2005) |
| 15 | EE | Lukás Sekanina,
Tughrul Arslan:
Evolvable Components-From Theory to Hardware Implementations.
Genetic Programming and Evolvable Machines 6(4): 461-462 (2005) |
| 2004 |
|---|
| 14 | EE | Lukás Sekanina,
Vladimír Drábek:
Theory and Applications of Evolvable Embedded Systems.
ECBS 2004: 186-194 |
| 13 | EE | Lukás Sekanina:
Evolutionary Design Space Exploration for Median Circuits.
EvoWorkshops 2004: 240-249 |
| 12 | EE | Lukás Sekanina,
Stepan Friedl:
On Routine Implementation of Virtual Evolvable Devices Using COMBO6.
Evolvable Hardware 2004: 63-70 |
| 11 | EE | Jim Torresen,
Jorgen W. Bakke,
Lukás Sekanina:
Recognizing Speed Limit Sign Numbers by Evolvable Hardware.
PPSN 2004: 682-691 |
| 10 | EE | Lukás Sekanina:
Evolving Constructors for Infinitely Growing Sorting Networks and Medians.
SOFSEM 2004: 314-323 |
| 9 | | Lukás Sekanina,
Stepan Friedl:
An Evolvable Combinational Unit for FPGAs.
Computers and Artificial Intelligence 23(5): (2004) |
| 2003 |
|---|
| 8 | EE | Lukás Sekanina:
From Implementations to a General Concept of Evolvable Machines.
EuroGP 2003: 424-433 |
| 7 | EE | Lukás Sekanina,
Richard Ruzicka:
Easily Testable Image Operators: The Class of Circuits Where Evolution Beats Engineers.
Evolvable Hardware 2003: 135-144 |
| 6 | EE | Lukás Sekanina:
Towards Evolvable IP Cores for FPGAs.
Evolvable Hardware 2003: 145-154 |
| 5 | EE | Lukás Sekanina:
Virtual Reconfigurable Circuits for Real-World Applications of Evolvable Hardware.
ICES 2003: 186-197 |
| 2002 |
|---|
| 4 | | Lukás Sekanina,
Jim Torresen:
Detection of Norwegian Speed Limit Signs.
ESM 2002: 337-340 |
| 3 | EE | Lukás Sekanina:
Image Filter Design with Evolvable Hardware.
EvoWorkshops 2002: 255-266 |
| 2000 |
|---|
| 2 | EE | Lukás Sekanina,
Azeddien M. Sllame:
Toward Uniform Approach to Design of Evolvable Hardware Based Systems.
FPL 2000: 814-817 |
| 1 | EE | Lukás Sekanina,
Vladimír Drábek:
Relation between Fault Tolerance and Reconfiguration in Cellular Systems.
IOLTW 2000: 25-30 |
