| 2007 |
|---|
| 13 | EE | Ciaran Toal,
Dwayne Burns,
Kieran McLaughlin,
Sakir Sezer,
Stephen O'Kane:
An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing.
AHS 2007: 613-618 |
| 12 | EE | Motasem Abdelghani,
Sakir Sezer,
Emi Garcia,
Jun Mu,
Ciaran Toal:
FPGA-Based Lookup Circuit for Session-Based IP Packet Classification.
AHS 2007: 619-624 |
| 11 | EE | Dwayne Burns,
Ciaran Toal,
Kieran McLaughlin,
Sakir Sezer,
Mike Hutton,
Kevin Cackovic:
An FPGA Based Memory Efficient Shared Buffer Implementation.
FPL 2007: 661-664 |
| 2006 |
|---|
| 10 | EE | Ciaran Toal,
Sakir Sezer:
Investigation into programmability for layer 2 protocol frame delineation architectures.
IPDPS 2006 |
| 9 | EE | Ciaran Toal,
Sakir Sezer,
Xin Yang:
A VLSI GFP Frame Delineation Circuit.
ISVLSI 2006: 454-455 |
| 2005 |
|---|
| 8 | EE | Ciaran Toal,
Sakir Sezer:
A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA.
AICT/SAPIR/ELETE 2005: 357-362 |
| 2004 |
|---|
| 7 | EE | Ciaran Toal,
Sakir Sezer:
The Implementation of Scalable ATM Frame Delineation Circuits.
ICT 2004: 1047-1056 |
| 6 | EE | Emi Garcia-Palacios,
Sakir Sezer,
Ciaran Toal,
Stephen Dawson:
Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access.
ICT 2004: 876-884 |
| 5 | EE | Sakir Sezer,
Ciaran Toal,
Emi Garcia,
V. Stewart:
A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling.
IPDPS 2004 |
| 2003 |
|---|
| 4 | EE | Ciaran Toal,
Sakir Sezer,
Xing Yu:
A Pipelined SoPC Architecture for 2.5 Gbps Network Processing.
FCCM 2003: 271-272 |
| 3 | EE | Brendan McAllister,
Sakir Sezer,
Ciaran Toal:
Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler.
FPL 2003: 1149-1152 |
| 2 | EE | Ciaran Toal,
Sakir Sezer:
A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET.
IPDPS 2003: 179 |
| 1 | EE | Ciaran Toal,
Sakir Sezer:
A 32-Bit SoPC Implementation of a P5.
ISCC 2003: 504-507 |
