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Philip Machanick

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2007
14EEJohn Shield, Peter Sutton, Philip Machanick: Dynamic Cache Switching in Reconfigurable Embedded Systems. FPL 2007: 111-116
13EEJohn Shield, Peter Sutton, Philip Machanick: Analysis of Kernel Effects on Optimisation Mismatch in Cache Reconfiguration. FPL 2007: 625-628
12EEPhilip Machanick: Design principles for a virtual multiprocessor. SAICSIT Conf. 2007: 76-82
2006
11EEKenneth M. Wilson, Philip Machanick: SecureTorrent: A Security Framework for File Swarming. Asia-Pacific Computer Systems Architecture Conference 2006: 538-544
2005
10EEPhilip Machanick: Peer Assessment for Action Learning of Data Structures and Algorithms. ACE 2005: 73-82
9EEPhilip Machanick: A distributed systems approach to secure Internet mail. Computers & Security 24(6): 492-499 (2005)
8EEPhilip Machanick: The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy. J. Comput. Sci. Technol. 20(5): 586-595 (2005)
2004
7EEPhilip Machanick: Initial Experiences with Dreamy Memory and the RAMpage Memory Hierarchy. Asia-Pacific Computer Systems Architecture Conference 2004: 146-159
2003
6EEPhilip Machanick, Zunaid Patel: L1 Cache and TLB Enhancements to the RAMpage Memory Hierarchy. Asia-Pacific Computer Systems Architecture Conference 2003: 305-319
5EEPhilip Machanick, Brynn Andrew: Latency Improvement in Virtual Multicasting. Asia-Pacific Computer Systems Architecture Conference 2003: 380-394
2001
4EEJudith L. Gersting, Peter B. Henderson, Philip Machanick, Yale N. Patt: Programming early considered harmful. SIGCSE 2001: 402-403
2000
3EERoss J. Anderson, Terry Bollinger, Doug Brown, Enrique Draier, Philip Machanick, Gary McGraw, Nancy R. Mead, Arthur B. Pyster, Howard Schmidt, Timothy J. Shimeall: Roundtable on Information Security Policy. IEEE Software 17(5): (2000)
2 Philip Machanick, Brynn Andrew: Virtual multicasting as an example of information mass transit. South African Computer Journal 26: 252-255 (2000)
1998
1EEPhilip Machanick, Pierre Salverda, Lance Pompe: Hardware-Software Trade-Offs in a Direct Rambus Implementation of the RAMpage Memory Hierarchy. ASPLOS 1998: 105-114

Coauthor Index

1Ross J. Anderson [3]
2Brynn Andrew [2] [5]
3Terry Bollinger [3]
4Doug Brown [3]
5Enrique Draier [3]
6Judith L. Gersting [4]
7Peter B. Henderson [4]
8Gary McGraw [3]
9Nancy R. Mead [3]
10Zunaid Patel [6]
11Yale N. Patt [4]
12Lance Pompe [1]
13Arthur B. Pyster [3]
14Pierre Salverda [1]
15Howard Schmidt [3]
16John Shield [13] [14]
17Timothy J. Shimeall [3]
18Peter Sutton [13] [14]
19Kenneth M. Wilson [11]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)