| 2008 |
|---|
| 58 | EE | Jehangir Khan,
Smaïl Niar,
Atika Rivenq,
Yassin Elhillali,
Jean-Luc Dekeyser:
An MPSoC architecture for the Multiple Target Tracking application in driver assistant system.
ASAP 2008: 126-131 |
| 57 | EE | Sebastien Revol,
Safouan Taha,
François Terrier,
Alain Clouard,
Sébastien Gérard,
Ansgar Radermacher,
Jean-Luc Dekeyser:
Unifying HW Analysis and SoC Design Flows by Bridging Two Key Standards: UML and IP-XACT.
DIPES 2008: 69-78 |
| 56 | EE | Imran Rafiq Quadri,
Samy Meftali,
Jean-Luc Dekeyser:
MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs.
ESTImedia 2008: 47-52 |
| 55 | EE | Adolf Abdallah,
Abdoulaye Gamatié,
Jean-Luc Dekeyser:
MARTE-based Design of a Multimedia Application and Formal Analysis.
FDL 2008: 160-166 |
| 54 | EE | Imran Rafiq Quadri,
Pierre Boulet,
Samy Meftali,
Jean-Luc Dekeyser:
Using an MDE Approach for Modeling of Interconnection Networks.
ISPAN 2008: 289-294 |
| 53 | EE | Abdoulaye Gamatié,
Éric Rutten,
Huafeng Yu,
Pierre Boulet,
Jean-Luc Dekeyser:
Modeling and Formal Validation of High-Performance Embedded Systems.
ISPDC 2008: 215-222 |
| 52 | EE | Julien Taillard,
Frédéric Guyomarc'h,
Jean-Luc Dekeyser:
A Graphical Framework for High Performance Computing Using An MDE Approach.
PDP 2008: 165-173 |
| 2007 |
|---|
| 51 | EE | Philippe Marquet,
Simon Duquennoy,
Sébastien Le Beux,
Samy Meftali,
Jean-Luc Dekeyser:
Massively parallel processing on a chip.
Conf. Computing Frontiers 2007: 277-286 |
| 50 | | Huafeng Yu,
Abdoulaye Gamatié,
Éric Rutten,
Jean-Luc Dekeyser:
Model Transformations from a Data Parallel Formalism towards Synchronous Languages.
FDL 2007: 255-260 |
| 49 | EE | Safouan Taha,
Ansgar Radermacher,
Sébastien Gérard,
Jean-Luc Dekeyser:
MARTE: UML-based Hardware Design from Modelling to Simulation.
FDL 2007: 274-279 |
| 48 | EE | Sébastien Le Beux,
Philippe Marquet,
Jean-Luc Dekeyser:
A Design Flow to Map Parallel Applications onto FPGAs.
FPL 2007: 605-608 |
| 47 | EE | Éric Piel,
Philippe Marquet,
Jean-Luc Dekeyser:
Model Transformations for the Compilation of Multi-processor Systems-on-Chip.
GTTSE 2007: 459-473 |
| 46 | EE | Rabie Ben Atitallah,
Smaïl Niar,
Samy Meftali,
Jean-Luc Dekeyser:
An MPSoC Performance Estimation Framework Using Transaction Level Modeling.
RTCSA 2007: 525-533 |
| 45 | | Sébastien Le Beux,
Philippe Marquet,
Jean-Luc Dekeyser:
Multiple Abstraction Views of FPGA to Map Parallel Applications.
ReCoSoC 2007: 90-97 |
| 44 | EE | Safouan Taha,
Ansgar Radermacher,
Sebastien Gerard,
Jean-Luc Dekeyser:
An Open Framework for Detailed Hardware Modeling.
SIES 2007: 118-125 |
| 2006 |
|---|
| 43 | EE | Rabie Ben Atitallah,
Smaïl Niar,
Alain Greiner,
Samy Meftali,
Jean-Luc Dekeyser:
Estimating Energy Consumption for an MPSoC Architectural Exploration.
ARCS 2006: 298-310 |
| 42 | EE | Sébastien Le Beux,
Philippe Marquet,
Ouassila Labbani,
Jean-Luc Dekeyser:
FPGA Implementation of Embedded Cruise Control and Anti-Collision Radar.
DSD 2006: 280-287 |
| 41 | EE | Ouassila Labbani,
Éric Rutten,
Jean-Luc Dekeyser,
Pierre Boulet:
UML2 Profile for Modeling Controlled Data Parallel Applications.
FDL 2006: 359-367 |
| 40 | EE | Éric Piel,
Philippe Marquet,
Julien Soula,
Jean-Luc Dekeyser:
Real-time systems for multiprocessor architectures.
IPDPS 2006 |
| 39 | EE | Ouassila Labbani,
Éric Rutten,
Jean-Luc Dekeyser:
Safe Design Methodology for an Intelligent Cruise Control System with GPS.
VTC Fall 2006: 1-5 |
| 38 | EE | Ahmad Chadi Aljundi,
Jean-Luc Dekeyser,
M. Tahar Kechadi,
Isaac D. Scherson:
A universal performance factor for multi-criteria evaluation of multistage interconnection networks.
Future Generation Comp. Syst. 22(7): 794-804 (2006) |
| 2005 |
|---|
| 37 | EE | J. Vennin,
S. Penain,
Luc Charest,
Samy Meftali,
Jean-Luc Dekeyser:
Embed Scripting inside SystemC.
FDL 2005: 373-385 |
| 36 | EE | Lossan Bonde,
Pierre Boulet,
Jean-Luc Dekeyser:
Traceability and Interoperability in Models Transformations.
FDL 2005: 543-555 |
| 35 | EE | Ouassila Labbani,
Jean-Luc Dekeyser,
Pierre Boulet:
Mode-Automata Based Methodology for Scade.
HSCC 2005: 386-401 |
| 34 | EE | Samy Meftali,
Jean-Luc Dekeyser,
Isaac D. Scherson:
Scalable Multistage Network for Multiprocessor System-on-Chip Design.
ISPAN 2005: 352-357 |
| 33 | EE | Arnaud Cuccuru,
Jean-Luc Dekeyser,
Philippe Marquet,
Pierre Boulet:
Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies.
MoDELS 2005: 445-459 |
| 32 | EE | Éric Piel,
Philippe Marquet,
Julien Soula,
Jean-Luc Dekeyser:
Asymmetric Scheduling and Load Balancing for Real-Time on Linux SMP.
PPAM 2005: 896-903 |
| 31 | | Pierre Boulet,
Arnaud Cuccuru,
Jean-Luc Dekeyser,
Ashish Meena:
Model Driven Engineering for Regular MPSoC Co-design.
ReCoSoC 2005: 129-136 |
| 2004 |
|---|
| 30 | EE | Lossan Bonde,
Cédric Dumoulin,
Jean-Luc Dekeyser:
Metamodels and MDA Transformations for Embedded Systems.
FDL 2004: 240-252 |
| 29 | EE | Arnaud Cuccuru,
Pierre Boulet,
Jean-Luc Dekeyser:
Regular Hardware Architecture Modeling with UML2.
FDL 2004: 289-301 |
| 28 | EE | E. Turbatu,
Samy Meftali,
Smaïl Niar,
Jean-Luc Dekeyser:
An automatic communication synthesis for high level SOC desing using transaction level modelling (poster).
FDL 2004: 378-380 |
| 27 | EE | M. Samyn,
Samy Meftali,
Jean-Luc Dekeyser:
MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications.
FDL 2004: 452-463 |
| 26 | EE | Samy Meftali,
Jean-Luc Dekeyser:
An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design.
IWSOC 2004: 55-58 |
| 25 | EE | Ahmad Chadi Aljundi,
Jean-Luc Dekeyser:
The Effect of the Degree of Multistage Interconnection Networks on their Performance: The Case of Delta and Over-Sized Delta Networks.
PDP 2004: 72- |
| 24 | | Samy Meftali,
Jean-Luc Dekeyser:
SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool.
Virtual Enterprises and Collaborative Networks 2004: 387-394 |
| 2003 |
|---|
| 23 | EE | Cédric Dumoulin,
Jean-Luc Dekeyser,
Boris Kokoszko,
S. Pulon,
G. Cristau:
Interoperability between Design and Simulation Tools using Model Transformation Techniques.
FDL 2003: 274-285 |
| 22 | EE | Pierre Boulet,
Jean-Luc Dekeyser,
Cédric Dumoulin,
Philippe Marquet:
MDA for SoC Design, Intensive Signal Processing Experiment.
FDL 2003: 309-317 |
| 21 | EE | Ahmad Chadi Aljundi,
Jean-Luc Dekeyser,
M. Tahar Kechadi,
Isaac D. Scherson:
A Study of an Evaluation Methodology for Unbuffered Multistage Interconnection Networks.
IPDPS 2003: 277 |
| 20 | | Ahmad Chadi Aljundi,
Jean-Luc Dekeyser,
Isaac D. Scherson:
An Interconnection Networks Comparative Performance Evaluation Methodology: Delta and Over-Sized Delta Networks.
ISCA PDCS 2003: 1-8 |
| 19 | | Abdelkader Amar,
Pierre Boulet,
Jean-Luc Dekeyser,
T. Theeuwen:
Distributed Process Networks - Using Half FIFO Queues in CORBA.
PARCO 2003: 31-38 |
| 2002 |
|---|
| 18 | EE | Florent Devin,
Pierre Boulet,
Jean-Luc Dekeyser,
Philippe Marquet:
GASPARD - A Visual Parallel Programming Environment.
PARELEC 2002: 145-150 |
| 2001 |
|---|
| 17 | EE | Julien Soula,
Philippe Marquet,
Alain Demeure,
Jean-Luc Dekeyser:
Compilation Principle of a Specification Language Dedicated to Signal Processing.
PaCT 2001: 358-370 |
| 2000 |
|---|
| 16 | EE | Emmanuel Cagniot,
Jean-Luc Dekeyser,
Pierre Boulet,
Thomas Brandes,
Francis Piriou,
Georges Marques:
Parallelization of a 3D Magnetostatic Code Using High Performance Fortran.
PARELEC 2000: 181-185 |
| 15 | EE | Emmanuel Cagniot,
Thomas Brandes,
Jean-Luc Dekeyser,
Francis Piriou,
Pierre Boulet,
Stéphane Clénet:
High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns.
VECPAR 2000: 519-528 |
| 1998 |
|---|
| 14 | | Fabien Banse,
Jean-Luc Dekeyser,
Renaud Fauquembergue,
François Dessenne:
Implementation of a Bi-Parallel Monte Carlo Device Simulation on Two Architectures.
HPCN Europe 1998: 193-202 |
| 13 | | Dominique Sueur,
Jean-Luc Dekeyser,
Philippe Marquet:
DPFS: A Data-Parallel File System Environment.
HPCN Europe 1998: 940-942 |
| 12 | | Cyril Fonlupt,
Philippe Marquet,
Jean-Luc Dekeyser:
Data-Parallel Load Balancing Strategies.
Parallel Computing 24(11): 1665-1684 (1998) |
| 1997 |
|---|
| 11 | | Jean-Luc Dekeyser,
Dominique Sueur:
Data Parallel File System.
PPSC 1997 |
| 10 | | Jean-Luc Dekeyser,
Christian Lefebvre:
Step By Step Transformation of a Fortran 90 Program in HPF, using HPF-Builder.
PPSC 1997 |
| 9 | | M. Tahar Kechadi,
Jean-Luc Dekeyser:
Analysis and Simulation of an Out-Of-Order Execution Model in Vector Multiprocessor Systems.
Parallel Computing 23(13): 1963-1986 (1997) |
| 1996 |
|---|
| 8 | | Dominique Sueur,
Jean-Luc Dekeyser:
Dynamic Redistribution on Heterogeneous Parallel Computers.
Euro-Par, Vol. I 1996: 173-177 |
| 7 | | Jean-Luc Dekeyser,
Philippe Marquet:
Supporting Irregular and Dynamic Computations in Data Parallel Languages.
The Data Parallel Programming Model 1996: 197-219 |
| 6 | | Jean-Luc Dekeyser,
Boris Kokoszko,
Jean-Luc Levaire,
Philippe Marquet:
Irregular Data-Parallel Objects in C++.
VECPAR 1996: 65-80 |
| 1994 |
|---|
| 5 | | Cyril Fonlupt,
Jean-Luc Dekeyser,
Philippe Marquet:
Dynamic Load Balancing on SIMD Data-Parallel Computers.
EUROSIM 1994: 219-226 |
| 4 | | Cyril Fonlupt,
Philippe Marquet,
Jean-Luc Dekeyser:
A Data-Parallel View of the Load Balancing - Experimental Results on MasPar MP-1.
HPCN 1994: 338-343 |
| 3 | | Jean-Luc Dekeyser,
Dominique Lazure,
Philippe Marquet:
A Geometrical Data-Parallel Language.
SIGPLAN Notices 29(4): 31-40 (1994) |
| 1993 |
|---|
| 2 | | Akram-Djellal Benalia,
Jean-Luc Dekeyser,
Philippe Marquet:
HelpDraw Graphical Environment: A Step Beyond Data Parallel Programming Languages.
HCI (2) 1993: 591-596 |
| 1990 |
|---|
| 1 | EE | Jean-Luc Dekeyser,
Philippe Marquet,
Ph. Pruex:
EVA: an explicit vector language.
SIGPLAN Notices 25(8): 53-71 (1990) |
