Kostas Siozios

K. Siozios

2008
22	EE	Kostas Siozios, Dimitrios Soudris: An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs. PATMOS 2008: 439-448
2007
21	EE	Kostas Siozios, Stelios Mamagkakis, Dimitrios Soudris, Antonios Thanailakis: Designing Heterogeneous FPGAs with Multiple SBs. ARC 2007: 91-96
20	EE	Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris: Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support. FPL 2007: 652-655
19	EE	Kostas Siozios, Dimitrios Soudris: A Novel Methodology for Temperature-Aware Placement and Routing of FPGAs. ISVLSI 2007: 55-60
18	EE	Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavlidis, Dimitrios Soudris: A software-supported methodology for designing high-performance 3D FPGA architectures. VLSI-SoC 2007: 54-59
2006
17	EE	K. Siozios, Konstantinos Tatas, Dimitrios Soudris, Antonios Thanailakis: A novel methodology for designing high-performance and low-energy FPGA routing architecture. FPGA 2006: 224
16	EE	Kostas Siozios, Dimitrios Soudris: Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures. FPL 2006: 1-4
15	EE	Kostas Siozios, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: Platform-based FPGA architecture: designing high-performance and low-power routing structure for realizing DSP applications. IPDPS 2006
14	EE	Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis: A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications. ISCAS 2006
13	EE	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources. PATMOS 2006: 403-414
12	EE	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis: Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique. VLSI-SoC 2006: 204-209
2005
11	EE	Dimitrios Soudris, Spiridon Nikolaidis, Stilianos Siskos, Konstantinos Tatas, K. Siozios, George Koutroumpezis, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Adonios Thanailakis: AMDREL: a novel low-energy FPGA architecture and supporting CAD tool design flow. ASP-DAC 2005: 3-4
10		K. Siozios, Konstantinos Tatas, George Koutroumpezis, D. J. Soudris, Adonios Thanailakis: An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. FPL 2005: 658-661
9		K. Siozios, Dimitrios Soudris, Adonios Thanailakis: A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. FPL 2005: 707-708
8	EE	K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: DAGGER: A Novel Generic Methodology for FPGA Bitstream Generation and Its Software Tool Implementation. IPDPS 2005
7	EE	Kostas Siozios, George Koutroumpezis, Konstantinos Tatas, Nikolaos Vassiliadis, Vasilios Kalenteridis, Haroula Pournara, Ilias Pappas, Dimitrios Soudris, Antonios Thanailakis, Spiridon Nikolaidis, Stilianos Siskos: A Novel FPGA Architecture and an Integrated Framework of CAD Tools for Implementing Applications. IEICE Transactions 88-D(7): 1369-1380 (2005)
6	EE	Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, Nikolaos Vassiliadis, Ilias Pappas, George Koutroumpezis, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris: A complete platform and toolset for system implementation on fine-grain reconfigurable hardware. Microprocessors and Microsystems 29(6): 247-259 (2005)
2004
5	EE	K. Siozios, George Koutroumpezis, Konstantinos Tatas, Dimitrios Soudris, Adonios Thanailakis: A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. FPL 2004: 1116-1118
4	EE	Vasilios Kalenteridis, Haroula Pournara, K. Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas, Spiridon Nikolaidis, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis: An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development. IPDPS 2004
2003
3	EE	Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis: Power-Efficient Implementations of Multimedia Applications on Reconfigurable Platforms. FPL 2003: 1032-1035
2	EE	Konstantinos Tatas, K. Siozios, Dimitrios Soudris, Adonios Thanailakis, Kostas Masselos, Konstantinos Potamianos, Spyros Blionas: Power Optimization Methdology for Multimedia Applications Implementation on Reconfigurable Platforms. PATMOS 2003: 430-439
1	EE	Konstantinos Tatas, K. Siozios, Nikolaos Vassiliadis, D. J. Soudris, Spiridon Nikolaidis, Stilianos Siskos, Adonios Thanailakis: FPGA Architecture Design and Toolset for Logic Implementation. PATMOS 2003: 607-616

Coauthor Index

1	Spyros Blionas	[2]
2	Vasilios Kalenteridis	[4] [6] [7] [11]
3	George Koutroumpezis	[4] [5] [6] [7] [8] [10] [11]
4	Stylianos Mamagkakis (Stelios Mamagkakis)	[21]
5	Kostas Masselos (Konstantinos Masselos)	[2]
6	Spiridon Nikolaidis	[1] [4] [6] [7] [11]
7	Ilias Pappas	[4] [6] [7] [11]
8	Vasilis F. Pavlidis	[18] [20]
9	Konstantinos Potamianos	[2]
10	Haroula Pournara	[4] [6] [7] [11]
11	Stilianos Siskos	[1] [4] [6] [7] [11]
12	Kostas Sotiriadis	[18] [20]
13	Dimitrios Soudris (D. J. Soudris)	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22]
14	Konstantinos Tatas (K. Tatas)	[1] [2] [3] [4] [5] [6] [7] [8] [10] [11] [15] [17]
15	Adonios Thanailakis (Antonios Thanailakis)	[1] [2] [3] [4] [5] [7] [8] [9] [10] [11] [12] [13] [14] [15] [17] [21]
16	Nikolaos Vassiliadis	[1] [6] [7] [11]