| 2009 |
|---|
| 10 | EE | Sumanta Chaudhuri:
Diagonal tracks in FPGAs: a performance evaluation.
FPGA 2009: 245-248 |
| 2008 |
|---|
| 9 | EE | Sumanta Chaudhuri,
Sylvain Guilley,
Philippe Hoogvorst,
Jean-Luc Danger,
Taha Beyrouthy,
Alin Razafindraibe,
Laurent Fesquet,
Marc Renaudin:
Physical Design of FPGA Interconnect to Prevent Information Leakage.
ARC 2008: 87-98 |
| 8 | EE | Sumanta Chaudhuri,
Sylvain Guilley,
Florent Flament,
Philippe Hoogvorst,
Jean-Luc Danger:
An 8x8 run-time reconfigurable FPGA embedded in a SoC.
DAC 2008: 120-125 |
| 7 | EE | Sumanta Chaudhuri,
Jean-Luc Danger,
Philippe Hoogvorst,
Sylvain Guilley:
Efficient tiling patterns for reconfigurable gate arrays.
FPGA 2008: 257 |
| 6 | EE | Sylvain Guilley,
Sumanta Chaudhuri,
Jean-Luc Danger,
Laurent Sauvage,
Philippe Hoogvorst,
Maxime Nassar,
Tarik Graba,
Vinh-Nga Vong:
Place-and-Route Impact on the Security of DPL Designs in FPGAs.
HOST 2008: 26-32 |
| 5 | EE | Sumanta Chaudhuri,
Sylvain Guilley,
Philippe Hoogvorst,
Jean-Luc Danger:
Efficient tiling patterns for reconfigurable gate arrays.
SLIP 2008: 11-18 |
| 4 | EE | Philippe Hoogvorst,
Sylvain Guilley,
Sumanta Chaudhuri,
Jean-Luc Danger,
Taha Beyrouthy,
Laurent Fesquet:
A Reconfigurable Programmable Logic Block for a Multi-Style Asynchronous FPGA resistant to Side-Channel Attacks
CoRR abs/0809.3942: (2008) |
| 3 | EE | Sylvain Guilley,
Laurent Sauvage,
Philippe Hoogvorst,
Renaud Pacalet,
Guido Marco Bertoni,
Sumanta Chaudhuri:
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.
IEEE Trans. Computers 57(11): 1482-1497 (2008) |
| 2007 |
|---|
| 2 | EE | Sumanta Chaudhuri,
Jean-Luc Danger,
Sylvain Guilley:
Efficient Modeling and Floorplanning of Embedded-FPGA Fabric.
FPL 2007: 665-669 |
| 1 | | Philippe Hoogvorst,
Sylvain Guilley,
Sumanta Chaudhuri,
Alin Razafindraibe,
Taha Beyrouthy,
Laurent Fesquet:
A Reconfigurable Cell for a Multi-Style Asynchronous FPGA.
ReCoSoC 2007: 15-22 |
