DFT 1999:
Albuquerque,
NM,
USA
14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings.
IEEE Computer Society 1999, ISBN 0-7695-0325-X BibTeX
@proceedings{DBLP:conf/dft/1999,
title = {14th International Symposium on Defect and Fault-Tolerance in
VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM,
USA, Proceedings},
booktitle = {DFT},
publisher = {IEEE Computer Society},
year = {1999},
isbn = {0-7695-0325-X},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Session 1:
Yield I
Session 2:
Yield II
Session 3:
Testing Techniques
Session 4:
Built-In Self-Test Architectures
Session 5:
Fault Modeling and Simulation
- Stefano Bertazzoni, Gian-Carlo Cardarilli, D. Piergentili, Marcello Salmeri, Adelio Salsano, Domenico Di Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, M. Ricci, V. Bidoli, D. de Francesco, P. G. Picozza, A. Rovelli:
Failure Tests on 64 Mb SDRAM in Radiation Environment.
158-164
Electronic Edition (IEEE Computer Society DL) BibTeX
- Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu:
RAMSES: A Fast Memory Fault Simulator.
165-173
Electronic Edition (IEEE Computer Society DL) BibTeX
- Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi:
Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information.
174-180
Electronic Edition (IEEE Computer Society DL) BibTeX
- Firas Khadour, Xiaoling Sun:
Fast Signature Simulation for PPSFP Simulators.
181-
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 6:
Design for Testing
Session 7:
Self-Checking Processing Units and Systems
- Parag K. Lala, Anup Singh, Alvernon Walker:
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs.
238-246
Electronic Edition (IEEE Computer Society DL) BibTeX
- Cristiana Bolchini, Luigi Pomante, Donatella Sciuto, Fabio Salice:
A Synthesis Methodology Aimed at Improving the Quality of TSC Devices.
247-255
Electronic Edition (IEEE Computer Society DL) BibTeX
- W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Power Consumption in Fast Dividers Using Time Shared TMR.
256-264
Electronic Edition (IEEE Computer Society DL) BibTeX
- Vincenzo Piuri, Earl E. Swartzlander Jr.:
Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors.
265-273
Electronic Edition (IEEE Computer Society DL) BibTeX
- Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Vincenzo Piuri:
Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs.
274-
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 8:
Self-Checking Memories and Interconnections
- Kiattichai Saowapa, Haruhiko Kaneko, Eiji Fujiwara:
Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability.
284-292
Electronic Edition (IEEE Computer Society DL) BibTeX
- William D. Armitage, Jien-Chung Lo:
Erasure Error Correction with Hardware Detection.
293-301
Electronic Edition (IEEE Computer Society DL) BibTeX
- Gian-Carlo Cardarilli, Stefano Bertazzoni, Marcello Salmeri, Adelio Salsano, P. Marinucci:
Design of Fault-Tolerant Solid State Mass Memory.
302-310
Electronic Edition (IEEE Computer Society DL) BibTeX
- Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu:
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention.
311-318
Electronic Edition (IEEE Computer Society DL) BibTeX
- C. Wickman, Duncan G. Elliott, Bruce F. Cockburn:
Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking.
319-
Electronic Edition (IEEE Computer Society DL) BibTeX
Session 9:
Diagnosis
Session 10:
Reconfiguration
- Wenyi Feng, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi:
Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources.
368-376
Electronic Edition (IEEE Computer Society DL) BibTeX
- Abderrahim Doumar, Satoshi Kaneko, Hideo Ito:
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data.
377-385
Electronic Edition (IEEE Computer Society DL) BibTeX
- John Lach, William H. Mangione-Smith, Miodrag Potkonjak:
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures.
386-394
Electronic Edition (IEEE Computer Society DL) BibTeX
- Sumito Nakano, Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui:
Reconfiguration of Two-Dimensional Meshes Embedded in Faulty Hypercubes.
395-403
Electronic Edition (IEEE Computer Society DL) BibTeX
Copyright © Sat May 16 23:06:35 2009
by Michael Ley (ley@uni-trier.de)
