MTDT 2002:
Isle of Bendor,
France
10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France.
IEEE Computer Society 2002, ISBN 0-7695-1617-3 BibTeX
@proceedings{DBLP:conf/mtdt/2002,
title = {10th IEEE International Workshop on Memory Technology, Design,
and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France},
booktitle = {MTDT},
publisher = {IEEE Computer Society},
year = {2002},
isbn = {0-7695-1617-3},
bibsource = {DBLP, http://dblp.uni-trier.de}
}
Memory BIST Analysis and Application
Memory ECC and Soft Errors
High Reliability in Railway and Automotive Systems
Embedded Memory Yield Enhancement
Embedded Memory Systems and Test Optimization
Memory Test Strategies
Fault Modeling
EPROM/EEPROM Design
Process Technology and Reliability
- T. Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, D. Roy, B. Borot, N. Planes, S. Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond:
Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC).
157-162
Electronic Edition (link) BibTeX
- Mario R. Casu, Philippe Flatresse:
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI.
163-167
Electronic Edition (link) BibTeX
- R. Laffont, J. Razafindramora, P. Canet, Rachid Bouchakour, J. M. Mirabel:
Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact.
168-176
Electronic Edition (link) BibTeX
Advanced Memory Technologies Panel
Copyright © Sat May 16 23:30:58 2009
by Michael Ley (ley@uni-trier.de)
