Yen-Lin Peng

2005
2	EE	Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu: A BIST Scheme for FPGA Interconnect Delay Faults. VTS 2005: 201-206
2004
1	EE	Yen-Lin Peng, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu: An Application-Independent Delay Testing Methodology for Island-Style FPGA. DFT 2004: 478-486

Coauthor Index

1	Chih-Tsun Huang	[1] [2]
2	Jing-Jia Liou	[1] [2]
3	Chun-Chieh Wang	[2]
4	Cheng-Wen Wu	[1] [2]