IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 7

Volume 7, Number 1, March 1999

• Ganesh Lakshminarayana, Anand Raghunathan, Niraj K. Jha, Sujit Dey:
  Power management in high-level synthesis. 7-15
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• Liqiong Wei, Zhanping Chen, Kaushik Roy, Mark C. Johnson, Yibin Ye, Vivek De:
  Design and optimization of dual-threshold circuits for low-voltage low-power applications. 16-24
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• J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, T. F. Chen:
  Segmented bus design for low-power systems. 25-29
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• Ganesh Gopalakrishnan, Prabhakar Kudva, Erik Brunvand:
  Peephole optimization of asynchronous macromodule networks. 30-37
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• Wayne P. Burleson, Jason Ko, Douglas Niehaus, Krithi Ramamritham, John A. Stankovic, Gary Wallace, Charles C. Weems:
  The spring scheduling coprocessor: a scheduling accelerator. 38-47
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• Tong Liu, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi:
  Test generation and scheduling for layout-based detection of bridge faults in interconnects. 48-55
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• Gauthier Lafruit, Francky Catthoor, Jan Cornelis, Hugo De Man:
  An efficient VLSI architecture for 2-D wavelet image coding with novel image scan. 56-68
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• George Karypis, Rajat Aggarwal, Vipin Kumar, Shashi Shekhar:
  Multilevel hypergraph partitioning: applications in VLSI domain. 69-79
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• Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
  The memory/logic interface in FPGAs with large embedded memory arrays. 80-91
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• Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha:
  COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems. 92-104
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• Fernando De Bernardinis, Roberto Roncella, Roberto Saletti, Pierangelo Terreni, Graziano Bertini:
  An efficient VLSI architecture for real-time additive synthesis of musical signals. 105-110
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• Victor V. Zyuban, Peter M. Kogge:
  Application of STD to latch-power estimation. 111-115
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• Wang-Dauh Tseng, Kuochen Wang:
  Fuzzy-based CMOS circuit partitioning in built-in current testing. 116-120
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• Shivaling S. Mahant-Shetti, Poras T. Balsara, Carl Lemonds:
  High performance low power array multiplier using temporal tiling. 121-124
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• Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan:
  Computation of lower bounds for switching activity using decision theory. 125-129
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• C.-Y. Wang, K. Roy:
  An activity-driven encoding scheme for power optimization in microprogrammed control unit. 130-134
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• Rong Lin, Stephan Olariu:
  Efficient VLSI architectures for Columnsort. 135-138
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• Hiroyuki Mizuno, Koichiro Ishibashi:
  A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. 139-144
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• F. Mu, C. Svensson:
  A layout-based schematic method for very high-speed CMOS cell design. 144-148
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Volume 7, Number 2, June 1999

• Uwe Sparmann, H. Mueller, Sudhakar M. Reddy:
  Universal delay test sets for logic networks. 156-166
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• Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith:
  Timing constraints for high-speed counterflow-clocked pipelining. 167-173
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• Tom Chen, Glen Sunada, Jain Jin:
  COBRA: a 100-MOPS single-chip programmable and expandable FFT. 174-182
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• Minesh B. Amin, Bapiraju Vinnakota:
  Data parallel fault simulation. 183-190
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• P. Chow, Soon Ong Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja:
  The design of an SRAM-based field-programmable gate array. I. Architecture. 191-197
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• Tracy C. Denk, Keshab K. Parhi:
  Two-dimensional retiming [VLSI design]. 198-211
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• Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
  A coding framework for low-power address and data busses. 212-221
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• Valery Sklyarov:
  Hierarchical finite-state machines and their use for digital control. 222-228
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• S. Dutta, W. Wolf:
  A circuit-driven design methodology for video signal-processing datapath elements. 229-240
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• Chung-Yu Wu, Hsin-Chin Jiang:
  An improved BJT-based silicon retina with tunable image smoothing capability. 241-248
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• Seong-Hwan Cho, Thucydides Xanthopoulos, Anantha P. Chandrakasan:
  A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning. 249-257
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• Koen Danckaert, Kostas Masselos, Francky Catthoor, Hugo De Man, Constantinos E. Goutis:
  Strategy for power-efficient design of parallel systems. 258-265
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• Christos A. Papachristou, Mehrdad Nourani, Mark Spining:
  A multiple clocking scheme for low-power RTL design. 266-276
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• Vamsi Krishna, N. Ranganathan, Abdel Ejnioui:
  A tree-matching chip. 277-280
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• Chih-Yuang Su, Shih-Am Hwang, Po-Song Chen, Cheng-Wen Wu:
  An improved Montgomery's algorithm for high-speed RSA public-key cryptosystem. 280-284
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Volume 7, Number 3, September 1999

• C. Chakrabarti, C. Mumford:
  Efficient realizations of encoders and decoders based on the 2-D discrete wavelet transform. 289-298
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• B. Bosi, Guy Bois, Yvon Savaria:
  Reconfigurable pipelined 2-D convolvers for fast digital signal processing. 299-308
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• Preeti Ranjan Panda, Nikil D. Dutt:
  Low-power memory mapping through reducing address bus activity. 309-320
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• P. Chow, Soon Ong Seo, J. Rose, K. Chung, G. Paez-Monzon, I. Rahardja:
  The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. 321-330
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• Chittaranjan A. Mandal, P. P. Chakrabarti, Sujoy Ghose:
  A design space exploration scheme for data-path synthesis. 331-338
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• M. Inamori, Jiro Naganuma, Makoto Endo:
  A memory-based architecture for MPEG2 system protocol LSIs. 339-344
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• Yuan-Hau Yeh, Chen-Yi Lee:
  Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms. 345-358
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• Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj:
  Information-theoretic bounds on average signal transition activity [VLSI systems]. 359-368
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• Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni:
  VLSI architectures for turbo codes. 369-379
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• Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou:
  A structure-oriented power modeling technique for macrocells. 380-391
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• Michele Favalli, Cecilia Metra:
  Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing. 392-396
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Volume 7, Number 4, December 1999

• Douglas M. Blough, Fadi J. Kurdahi, Seong Yong Ohm:
  High-level synthesis of recoverable VLSI microarchitectures. 401-410
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• Min Xu, Fadi J. Kurdahi:
  Accurate prediction of quality metrics for logic level designs targeted toward lookup-table-based FPGAs. 411-418
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• Smita Bakshi, Daniel D. Gajski:
  Partitioning and pipelining for performance-constrained hardware/software systems. 419-432
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• Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Hugo De Man:
  Minimizing the required memory bandwidth in VLSI system realizations. 433-441
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• Yehea I. Ismail, Eby G. Friedman, José Luis Neves:
  Figures of merit to characterize the importance of on-chip inductance. 442-449
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• Keshab K. Parhi:
  Low-energy CSMT carry generators and binary adders. 450-462
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• Manish Goel, Naresh R. Shanbhag:
  Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. 463-476
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• Chung-Sheng Li, Kumar N. Sivarajan, David G. Messerschmitt:
  Statistical analysis of timing rules for high-speed synchronous VLSI systems. 477-482
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• Kenneth Y. Yun, Ayoob E. Dooply:
  Pausible clocking-based heterogeneous systems. 482-488
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• Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen:
  EmGen-a module generator for logic emulation applications. 488-492
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• Kostas Masselos, Panagiotis Merakos, Thanos Stouraitis, Constantinos E. Goutis:
  Novel techniques for bus power consumption reduction in realizations of sum-of-product computation. 492-497
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