| 2008 |
|---|
| 8 | EE | Xiaoxiao Wang,
Mohammad Tehranipoor,
Ramyanshu Datta:
Path-RO: a novel on-chip critical path delay measurement under process variations.
ICCAD 2008: 640-646 |
| 7 | EE | Ramyanshu Datta,
Jacob A. Abraham,
Abdulkadir Utku Diril,
Abhijit Chatterjee,
Kevin J. Nowka:
Performance-Optimized Design for Parametric Reliability.
J. Electronic Testing 24(1-3): 129-141 (2008) |
| 6 | EE | Ramyanshu Datta,
Ravi Gupta,
Antony Sebastine,
Jacob A. Abraham,
Manuel A. d'Abreu:
Controllability of Static CMOS Circuits for Timing Characterization.
J. Electronic Testing 24(5): 481-496 (2008) |
| 2006 |
|---|
| 5 | EE | Ramyanshu Datta,
Jacob A. Abraham,
Abdulkadir Utku Diril,
Abhijit Chatterjee,
Kevin J. Nowka:
Adaptive Design for Performance-Optimized Robustness.
DFT 2006: 3-11 |
| 4 | EE | Ramyanshu Datta,
Gary D. Carpenter,
Kevin J. Nowka,
Jacob A. Abraham:
A Scheme for On-Chip Timing Characterization.
VTS 2006: 24-29 |
| 2004 |
|---|
| 3 | EE | Ramyanshu Datta,
Antony Sebastine,
Ashwin Raghunathan,
Jacob A. Abraham:
On-chip delay measurement for silicon debug.
ACM Great Lakes Symposium on VLSI 2004: 145-148 |
| 2 | | Ramyanshu Datta,
Jacob A. Abraham,
Robert K. Montoye,
Wendy Belluomini,
Hung C. Ngo,
Chandler McDowell,
Jente B. Kuang,
Kevin J. Nowka:
A low latency and low power dynamic Carry Save Adder.
ISCAS (2) 2004: 477-480 |
| 1 | EE | Ramyanshu Datta,
Ravi Gupta,
Antony Sebastine,
Jacob A. Abraham,
Manuel A. d'Abreu:
Tri-Scan: A Novel DFT Technique for CMOS Path Delay Fault Testing.
ITC 2004: 1118-1127 |
