2008 |
23 | EE | Shianling Wu,
Laung-Terng Wang,
Zhigang Jiang,
Jiayong Song,
Boryau Sheu,
Xiaoqing Wen,
Michael Hsiao,
James Chien-Mo Li,
Jiun Lang Huang,
Ravi Apte:
On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.
DFT 2008: 143-151 |
22 | EE | Laung-Terng Wang,
Charles E. Stroud,
Kwang-Ting (Tim) Cheng:
Logic Testing.
Wiley Encyclopedia of Computer Science and Engineering 2008 |
21 | EE | Laung-Terng Wang,
Xiaoqing Wen,
Shianling Wu,
Zhigang Wang,
Zhigang Jiang,
Boryau Sheu,
Xinli Gu:
VirtualScan: Test Compression Technology Using Combinational Logic and One-Pass ATPG.
IEEE Design & Test of Computers 25(2): 122-130 (2008) |
20 | EE | Xiaoqing Wen,
Kohei Miyase,
Tatsuya Suzuki,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja,
Kozo Kinoshita:
Low Capture Switching Activity Test Generation for Reducing IR-Drop in At-Speed Scan Testing.
J. Electronic Testing 24(4): 379-391 (2008) |
2007 |
19 | EE | B. Cheon,
E. Lee,
Laung-Terng Wang,
Xiaoqing Wen,
P. Hsu,
J. Cho,
J. Park,
H. Chao,
Shianling Wu:
At-Speed Logic BIST for IP Cores
CoRR abs/0710.4645: (2007) |
18 | EE | Xiaoqing Wen,
Seiji Kajihara,
Kohei Miyase,
Tatsuya Suzuki,
Kewal K. Saluja,
Laung-Terng Wang,
Kozo Kinoshita:
A Novel ATPG Method for Capture Power Reduction during Scan Testing.
IEICE Transactions 90-D(9): 1398-1405 (2007) |
2006 |
17 | EE | Xiaoqing Wen,
Kohei Miyase,
Tatsuya Suzuki,
Yuta Yamato,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja:
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.
ICCD 2006 |
16 | EE | Xiaoqing Wen,
Seiji Kajihara,
Kohei Miyase,
Tatsuya Suzuki,
Kewal K. Saluja,
Laung-Terng Wang,
Khader S. Abdel-Hafez,
Kozo Kinoshita:
A New ATPG Method for Efficient Capture Power Reduction During Scan Testing.
VTS 2006: 58-65 |
15 | EE | Xiaoqing Wen,
Seiji Kajihara,
Kohei Miyase,
Yuta Yamato,
Kewal K. Saluja,
Laung-Terng Wang,
Kozo Kinoshita:
A Per-Test Fault Diagnosis Method Based on the X-Fault Model.
IEICE Transactions 89-D(11): 2756-2765 (2006) |
14 | EE | Xiaoqing Wen,
Yoshiyuki Yamashita,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja,
Kozo Kinoshita:
A New Method for Low-Capture-Power Test Generation for Scan Testing.
IEICE Transactions 89-D(5): 1679-1686 (2006) |
2005 |
13 | EE | B. Cheon,
E. Lee,
Laung-Terng Wang,
Xiaoqing Wen,
P. Hsu,
J. Cho,
J. Park,
H. Chao,
Shianling Wu:
At-Speed Logic BIST for IP Cores.
DATE 2005: 860-861 |
12 | EE | Laung-Terng Wang,
Xiaoqing Wen,
Po-Ching Hsu,
Shianling Wu,
Jonhson Guo:
At-Speed Logic BIST Architecture for Multi-Clock Designs.
ICCD 2005: 475-478 |
11 | EE | Xiaoqing Wen,
Yoshiyuki Yamashita,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja,
Kozo Kinoshita:
On Low-Capture-Power Test Generation for Scan Testing.
VTS 2005: 265-270 |
10 | EE | Xiaoqing Wen,
Tatsuya Suzuki,
Seiji Kajihara,
Kohei Miyase,
Yoshihiro Minamoto,
Laung-Terng Wang,
Kewal K. Saluja:
Efficient Test Set Modification for Capture Power Reduction.
J. Low Power Electronics 1(3): 319-330 (2005) |
2004 |
9 | EE | Xiaoqing Wen,
Tokiharu Miyoshi,
Seiji Kajihara,
Laung-Terng Wang,
Kewal K. Saluja,
Kozo Kinoshita:
On per-test fault diagnosis using the X-fault model.
ICCAD 2004: 633-640 |
8 | EE | Laung-Terng Wang,
Khader S. Abdel-Hafez,
Shianling Wu,
Xiaoqing Wen,
Hiroshi Furukawa,
Fei-Sheng Hsu,
Shyh-Horng Lin,
Sen-Wei Tsai:
VirtualScan: A New Compressed Scan Technology for Test Cost Reduction.
ITC 2004: 916-925 |
1988 |
7 | | Laung-Terng Wang,
Edward J. McCluskey:
Linear Feedback Shift Register Design Using Cyclic Codes.
IEEE Trans. Computers 37(10): 1302-1306 (1988) |
6 | EE | Laung-Terng Wang,
Edward J. McCluskey:
Hybrid designs generating maximum-length sequences.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 91-99 (1988) |
5 | EE | Laung-Terng Wang,
Edward J. McCluskey:
Circuits for pseudoexhaustive test pattern generation.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(10): 1068-1080 (1988) |
1986 |
4 | | Laung-Terng Wang,
Edward J. McCluskey:
Circuits for Pseudo-Exhaustive Test Pattern Generation.
ITC 1986: 25-37 |
3 | | Laung-Terng Wang,
Edward J. McCluskey:
A Hybrid Design of Maximum-Length Sequence Generators.
ITC 1986: 38-47 |
2 | | Laung-Terng Wang,
Edward J. McCluskey:
Condensed Linear Feedback Shift Register (LFSR) Testing - A Pseudoexhaustive Test Technique.
IEEE Trans. Computers 35(4): 367-370 (1986) |
1984 |
1 | | Zuhi Sun,
Laung-Terng Wang:
Self-Testing of Embedded RAMs.
ITC 1984: 148-156 |