2007 |
22 | EE | Muhammad Usama,
Tad A. Kwasniewski:
A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS Technology.
ISCAS 2007: 3047-3050 |
2006 |
21 | EE | Miao Li,
Tad A. Kwasniewski,
Shoujun Wang:
A 0.18µm CMOS Receiver with Decision-feedback Equalization for Backplane Applications.
APCCAS 2006: 1039-1042 |
20 | EE | Qingjin Du,
Jingcheng Zhuang,
Tad A. Kwasniewski:
A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider.
CCECE 2006: 701-704 |
19 | EE | Wm. Bereza,
Yuming Tao,
Shoujun Wang,
Tad A. Kwasniewski,
Rakesh H. Patel:
PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations.
DAC 2006: 1013-1016 |
18 | EE | Miao Li,
Wenjie Huang,
Tad A. Kwasniewski,
Shoujun Wang:
A 0.18µm CMOS clock and data recovery circuit with extended operation range.
ISCAS 2006 |
17 | EE | Jingcheng Zhuang,
Qingjin Du,
Tad A. Kwasniewski:
An eye detection technique for clock and data recovery applications.
ISCAS 2006 |
2005 |
16 | EE | Miao Li,
Tad A. Kwasniewski,
Shoujun Wang,
Yuming Tao:
A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18µm CMOS technology.
ASP-DAC 2005: 679-682 |
15 | | Jingcheng Zhuang,
Qingjin Du,
Tad A. Kwasniewski:
A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO.
Circuits, Signals, and Systems 2005: 128-131 |
14 | EE | Miao Li,
Wenjie Huang,
Tad A. Kwasniewski,
Shoujun Wang:
A 0.18µm CMOS transceiver design for high-speed backplane data communications.
ISCAS (2) 2005: 1158-1161 |
13 | EE | Jing Chen,
Miao Li,
Tad A. Kwasniewski:
Decision feedback equalization for high-speed backplane data communications.
ISCAS (2) 2005: 1274-1277 |
12 | EE | S. I. Ahmed,
Tad A. Kwasniewski:
An all-digital data recovery circuit optimization using Matlab/Simulink.
ISCAS (5) 2005: 4485-4488 |
11 | EE | Charles E. Berndt,
Tad A. Kwasniewski:
A Review of Common Receive-End Adaptive Equalization Schemes and Algorithms for a High-Speed Serial Backplane.
IWSOC 2005: 149-153 |
10 | EE | Moeed Israr,
Tad A. Kwasniewski:
Turbo Codes - Digital IC Design.
IWSOC 2005: 341-346 |
9 | EE | Miao Li,
Peter Noel,
Tad A. Kwasniewski,
Shoujun Wang:
Decision Feedback Equalization with Quarter-Rate Clock Timing for High-Speed Backplane Data Communications.
IWSOC 2005: 500-502 |
8 | EE | Farhad Zarkeshvari,
Peter Noel,
Tad A. Kwasniewski:
PLL-Based Fractional-N Frequency Synthesizers.
IWSOC 2005: 85-91 |
2004 |
7 | EE | Arif A. Siddiqi,
Tad A. Kwasniewski:
2.4 GHz RF down-conversion mixers in standard CMOS technology.
ISCAS (4) 2004: 321-324 |
6 | | Muhammad Usama,
Tad A. Kwasniewski:
Design and comparison of CMOS Current Mode Logic latches.
ISCAS (4) 2004: 353-356 |
1999 |
5 | EE | Lizhong Sun,
Thierry Lepley,
Franck Nozahic,
Amaud Bellissant,
Tad A. Kwasniewski,
Bany Heim:
Reduced complexity, high performance digital delta-sigma modulator for fractional-N frequency synthesis.
ISCAS (2) 1999: 152-155 |
4 | EE | Lizhong Sun,
Tad A. Kwasniewski,
Kris Iniewski:
A quadrature output voltage controlled ring oscillator based on three-stage sub-feedback loops.
ISCAS (2) 1999: 176-179 |
1996 |
3 | EE | Bozena Kaminska,
Tad A. Kwasniewski,
Linda S. Milor,
G. Roberts,
P. Flahive,
Jérôme Wojcik:
Is High Frequency Analog DFT Possible?
VTS 1996: 214-215 |
1994 |
2 | EE | V. Szwarc,
L. Desormeaux,
W. Wong,
C. P. S. Yeung,
C. H. Chan,
Tad A. Kwasniewski:
A chip set for pipeline and parallel pipeline FFT architectures.
VLSI Signal Processing 8(3): 253-265 (1994) |
1991 |
1 | | P. Mohanraj,
David D. Falconer,
Tad A. Kwasniewski:
Baseband Trellis-Coded Modulation with Combined Equalization/Decoding for High Bit Rate Digital Subscriber Loops.
IEEE Journal on Selected Areas in Communications 9(6): 871-875 (1991) |