2008 |
44 | EE | Qiong Cai,
Josep M. Codina,
José González,
Antonio González:
A software-hardware hybrid steering mechanism for clustered microarchitectures.
IPDPS 2008: 1-12 |
43 | EE | Fernando Latorre,
José González,
Antonio González:
Efficient resources assignment schemes for clustered multithreaded processors.
IPDPS 2008: 1-12 |
42 | EE | José González,
Qiong Cai,
Pedro Chaparro,
Grigorios Magklis,
Ryan Rakvic,
Antonio González:
Thread fusion.
ISLPED 2008: 363-368 |
41 | EE | Enric Herrero,
José González,
Ramon Canal:
Distributed cooperative caching.
PACT 2008: 134-143 |
40 | EE | Qiong Cai,
José González,
Ryan Rakvic,
Grigorios Magklis,
Pedro Chaparro,
Antonio González:
Meeting points: using thread criticality to adapt multicore hardware to parallel regions.
PACT 2008: 240-249 |
2007 |
39 | EE | Michael F. P. O'Boyle,
François Bodin,
José González,
Lucian N. Vintan:
Topic 4 High-Performance Architectures and Compilers.
Euro-Par 2007: 235 |
38 | EE | Pedro Chaparro,
José González,
Grigorios Magklis,
Qiong Cai,
Antonio González:
Understanding the Thermal Implications of Multi-Core Architectures.
IEEE Trans. Parallel Distrib. Syst. 18(8): 1055-1065 (2007) |
37 | EE | Gregorio Bernabé,
Ricardo Fernández,
José M. García,
Manuel E. Acacio,
José González:
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology.
Parallel Computing 33(1): 54-72 (2007) |
2006 |
36 | EE | Grigorios Magklis,
Pedro Chaparro,
José González,
Antonio González:
Independent front-end and back-end dynamic voltage scaling for a GALS microarchitecture.
ISLPED 2006: 49-54 |
2005 |
35 | EE | Pedro Chaparro,
Grigorios Magklis,
José González,
Antonio González:
Distributing the Frontend for Temperature Reduction.
HPCA 2005: 61-70 |
34 | EE | Manuel E. Acacio,
José González,
José M. García,
José Duato:
A Two-Level Directory Architecture for Highly Scalable cc-NUMA Multiprocessors.
IEEE Trans. Parallel Distrib. Syst. 16(1): 67-79 (2005) |
33 | EE | Gregorio Bernabé,
José M. García,
José González:
Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions.
VLSI Signal Processing 41(2): 209-223 (2005) |
2004 |
32 | EE | Grigorios Magklis,
José González,
Antonio González:
Frontend Frequency-Voltage Adaptation for Optimal Energy-Delay^2.
ICCD 2004: 250-255 |
31 | EE | Pedro Chaparro,
José González,
Antonio González:
Thermal-Aware Clustered Microarchitectures.
ICCD 2004: 48-53 |
30 | EE | Fernando Latorre,
José González,
Antonio González:
Back-end assignment schemes for clustered multithreaded processors.
ICS 2004: 316-325 |
29 | EE | José González,
Fernando Latorre,
Antonio González:
Cache organizations for clustered microarchitectures.
WMPI 2004: 46-55 |
28 | EE | Teresa Monreal,
Víctor Viñals,
José González,
Antonio González,
Mateo Valero:
Late Allocation and Early Release of Physical Registers.
IEEE Trans. Computers 53(10): 1244-1259 (2004) |
27 | EE | Manuel E. Acacio,
José González,
José M. García,
José Duato:
An Architecture for High-Performance Scalable Shared-Memory Multiprocessors Exploiting On-Chip Integration.
IEEE Trans. Parallel Distrib. Syst. 15(8): 755-768 (2004) |
26 | EE | Javier Cuenca,
Domingo Giménez,
José González:
Architecture of an automatically tuned linear algebra library.
Parallel Computing 30(2): 187-210 (2004) |
2003 |
25 | EE | Juan L. Aragón,
José González,
Antonio González:
Power-Aware Control Speculation through Selective Throttling.
HPCA 2003: 103-112 |
24 | EE | José González,
Antonio González:
Dynamic Cluster Resizing.
ICCD 2003: 375- |
23 | EE | Javier Cuenca,
Domingo Giménez,
José González,
Jack Dongarra,
Kenneth Roche:
Automatic Optimisation of Parallel Linear Algebra Routines in Systems with Variable Load.
PDP 2003: 409-416 |
22 | EE | Gregorio Bernabé,
José M. García,
José González:
Reducing 3D Wavelet Transform Execution Time through the Streaming SIMD Extensions.
PDP 2003: 49-56 |
21 | EE | Javier Cuenca,
Luis-Pedro García,
Domingo Giménez,
José González,
Antonio M. Vidal:
Empirical Modelling of Parallel Linear Algebra Routines.
PPAM 2003: 169-174 |
2002 |
20 | EE | Gregorio Bernabé,
José González,
José M. García,
José Duato:
Memory Conscious 3D Wavelet Transform.
EUROMICRO 2002: 108-113 |
19 | EE | Juan L. Aragón,
José González,
Antonio González,
James E. Smith:
Dual path instruction processing.
ICS 2002: 220-229 |
18 | EE | Manuel E. Acacio,
José González,
José M. García,
José Duato:
The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors.
IEEE PACT 2002: 155-164 |
17 | EE | Manuel E. Acacio,
José González,
José M. García,
José Duato:
A Novel Approach to Reduce L2 Miss Latency in Shared-Memory Multiprocessors.
IPDPS 2002 |
16 | EE | Javier Cuenca,
Domingo Giménez,
José González:
Towards the Design of an Automatically Tuned Linear Algebra Library.
PDP 2002: 201- |
15 | EE | Manuel E. Acacio,
José González,
José M. García,
José Duato:
Reducing the Latency of L2 Misses in Shared-Memory Multiprocessors through On-Chip Directory Integration.
PDP 2002: 368-375 |
14 | EE | Manuel E. Acacio,
José González,
José M. García,
José Duato:
Owner prediction for accelerating cache-to-cache transfer misses in a cc-NUMA architecture.
SC 2002: 1-12 |
2001 |
13 | EE | Manuel E. Acacio,
José González,
José M. García,
José Duato:
A New Scalable Directory Architecture for Large-Scale Multiprocessors.
HPCA 2001: 97-106 |
12 | EE | Juan L. Aragón,
José González,
José M. García,
Antonio González:
Confidence Estimation for Branch Prediction Reversal.
HiPC 2001: 214-223 |
11 | | Juan L. Aragón,
José González,
José M. García,
Antonio González:
Selective Branch Prediction Reversal By Correlating with Data Values and Control Flow.
ICCD 2001: 228-233 |
10 | EE | José González,
Antonio González:
Control-Flow Speculation through Value Prediction.
IEEE Trans. Computers 50(12): 1362-1376 (2001) |
2000 |
9 | EE | Teresa Monreal,
Antonio González,
Mateo Valero,
José González,
Víctor Viñals:
Dynamic Register Renaming Through Virtual-Physical Registers.
J. Instruction-Level Parallelism 2: (2000) |
1999 |
8 | EE | José González,
Antonio González:
Control-Flow Speculation through Value Prediction for Superscalar Processors.
IEEE PACT 1999: 57-65 |
7 | EE | Teresa Monreal,
Antonio González,
Mateo Valero,
José González,
Víctor Viñals:
Delaying Physical Register Allocation through Virtual-Physical Registers.
MICRO 1999: 186- |
1998 |
6 | EE | Antonio González,
José González,
Mateo Valero:
Virtual-Physical Registers.
HPCA 1998: 175-184 |
5 | EE | José González,
Antonio González:
The Potential of Data Value Speculation to Boost ILP.
International Conference on Supercomputing 1998: 21-28 |
4 | | José González,
Antonio González:
Limits of Instruction Level Parallelism with Data Value Speculation.
VECPAR 1998: 452-465 |
1997 |
3 | | José González,
Antonio González:
Memory Address Prediction for Data Speculation.
Euro-Par 1997: 1084-1091 |
2 | EE | José González,
Antonio González:
Speculative Execution via Address Prediction and Data Prefetching.
International Conference on Supercomputing 1997: 196-203 |
1 | EE | Nigel P. Topham,
Antonio González,
José González:
The Design and Performance of a Conflict-Avoiding Cache.
MICRO 1997: 71-80 |