| 2007 |
|---|
| 9 | EE | Ruibing Lu,
Aiqun Cao,
Cheng-Kok Koh:
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.
IEEE Trans. VLSI Syst. 15(1): 69-79 (2007) |
| 2006 |
|---|
| 8 | EE | Aiqun Cao,
Ruibing Lu,
Chen Li,
Cheng-Kok Koh:
Postlayout optimization for synthesis of Domino circuits.
ACM Trans. Design Autom. Electr. Syst. 11(4): 797-821 (2006) |
| 2005 |
|---|
| 7 | EE | Ruibing Lu,
Aiqun Cao,
Cheng-Kok Koh:
Improving the scalability of SAMBA bus architecture.
ASP-DAC 2005: 1164-1167 |
| 6 | EE | Aiqun Cao,
Ruibing Lu,
Cheng-Kok Koh:
Post-layout logic duplication for synthesis of domino circuits with complex gates.
ASP-DAC 2005: 260-265 |
| 5 | EE | Aiqun Cao,
Naran Sirisantana,
Cheng-Kok Koh,
Kaushik Roy:
Synthesis of skewed logic circuits.
ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005) |
| 2004 |
|---|
| 4 | EE | Aiqun Cao,
Cheng-Kok Koh:
Post-layout logic optimization of domino circuits.
DAC 2004: 820-825 |
| 2003 |
|---|
| 3 | EE | Aiqun Cao,
Cheng-Kok Koh:
Non-Crossing OBDDs for Mapping to Regular Circuit Structures.
ICCD 2003: 338-343 |
| 2002 |
|---|
| 2 | EE | Aiqun Cao,
Naran Sirisantana,
Cheng-Kok Koh,
Kaushik Roy:
Synthesis of Selectively Clocked Skewed Logic Circuits.
ISQED 2002: 229-234 |
| 2001 |
|---|
| 1 | EE | Naran Sirisantana,
Aiqun Cao,
Shawn Davidson,
Cheng-Kok Koh,
Kaushik Roy:
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
ISLPED 2001: 267-270 |
