| 2007 |
|---|
| 6 | EE | Paul Gratz,
Karthikeyan Sankaralingam,
Heather Hanson,
Premkishore Shivakumar,
Robert G. McDonald,
Stephen W. Keckler,
Doug Burger:
Implementation and Evaluation of a Dynamically Routed Processor Operand Network.
NOCS 2007: 7-17 |
| 5 | EE | Paul Gratz,
Changkyu Kim,
Karthikeyan Sankaralingam,
Heather Hanson,
Premkishore Shivakumar,
Stephen W. Keckler,
Doug Burger:
On-Chip Interconnection Networks of the TRIPS Chip.
IEEE Micro 27(5): 41-50 (2007) |
| 2006 |
|---|
| 4 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Robert G. McDonald,
Rajagopalan Desikan,
Saurabh Drolia,
M. S. Govindan,
Paul Gratz,
Divya Gulati,
Heather Hanson,
Changkyu Kim,
Haiming Liu,
Nitya Ranganathan,
Simha Sethumadhavan,
Sadia Sharif,
Premkishore Shivakumar,
Stephen W. Keckler,
Doug Burger:
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.
MICRO 2006: 480-491 |
| 2003 |
|---|
| 3 | EE | Premkishore Shivakumar,
Stephen W. Keckler,
Charles R. Moore,
Doug Burger:
Exploiting Microarchitectural Redundancy For Defect Tolerance.
ICCD 2003: 481-488 |
| 2002 |
|---|
| 2 | EE | Premkishore Shivakumar,
Michael Kistler,
Stephen W. Keckler,
Doug Burger,
Lorenzo Alvisi:
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic.
DSN 2002: 389-398 |
| 1 | EE | M. S. Hrishikesh,
Doug Burger,
Stephen W. Keckler,
Premkishore Shivakumar,
Norman P. Jouppi,
Keith I. Farkas:
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays.
ISCA 2002: 14-24 |
