| 2008 |
|---|
| 10 | EE | Jiangjiang Liu,
Nihar R. Mahapatra:
The role of interconnects in the performance scalability of multicore architectures.
SoCC 2008: 21-24 |
| 2007 |
|---|
| 9 | EE | Peggy Israel Doerschuk,
Jiangjiang Liu,
Judith Mann:
Pilot summer camps in computing for middle school girls: from organization through assessment.
ITiCSE 2007: 4-8 |
| 2006 |
|---|
| 8 | EE | Jiangjiang Liu,
Krishnan Sundaresan,
Nihar R. Mahapatra:
Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction.
ACM Great Lakes Symposium on VLSI 2006: 111-114 |
| 7 | EE | Jiangjiang Liu,
Krishnan Sundaresan,
Nihar R. Mahapatra:
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses.
ICCD 2006 |
| 6 | EE | Jiangjiang Liu,
Brian Bell,
Tan Truong:
Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance.
IMSCCS (1) 2006: 389-396 |
| 2005 |
|---|
| 5 | EE | Jiangjiang Liu,
Krishnan Sundaresan,
Nihar R. Mahapatra:
Energy-Efficient Compressed Address Transmission.
VLSI Design 2005: 592-597 |
| 2004 |
|---|
| 4 | EE | Jiangjiang Liu,
Krishnan Sundaresan,
Nihar R. Mahapatra:
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.
ICCD 2004: 458-463 |
| 2003 |
|---|
| 3 | EE | Nihar R. Mahapatra,
Jiangjiang Liu,
Krishnan Sundaresan:
Hardware-Only Compression of Underutilized Address Buses: Design and Performance, Power, and Cost Analysis.
ICCD 2003: 234-239 |
| 2 | EE | Jiangjiang Liu,
Nihar R. Mahapatra,
Krishnan Sundaresan:
Hardware-Only Compression to Reduce Cost and Improve Utilization of Address Buses.
ISVLSI 2003: 220-221 |
| 2002 |
|---|
| 1 | EE | Nihar R. Mahapatra,
Jiangjiang Liu,
Krishnan Sundaresan:
The performance advantage of applying compression to the memory system.
MSP/ISMM 2002: 86-96 |
