| 2006 |
|---|
| 6 | EE | Saraju P. Mohanty,
N. Ranganathan,
Sunil K. Chappidi:
ILP models for simultaneous energy and transient power minimization during behavioral synthesis.
ACM Trans. Design Autom. Electr. Syst. 11(1): 186-212 (2006) |
| 2004 |
|---|
| 5 | EE | Saraju P. Mohanty,
Nagarajan Ranganathan,
Sunil K. Chappidi:
ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis.
VLSI Design 2004: 745-748 |
| 2003 |
|---|
| 4 | EE | Saraju P. Mohanty,
N. Ranganathan,
Sunil K. Chappidi:
Simultaneous peak and average power minimization during datapath scheduling for DSP processors.
ACM Great Lakes Symposium on VLSI 2003: 215-220 |
| 3 | EE | Saraju P. Mohanty,
N. Ranganathan,
Sunil K. Chappidi:
Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling.
ICCD 2003: 441-443 |
| 2 | EE | Saraju P. Mohanty,
N. Ranganathan,
Sunil K. Chappidi:
An ILP-based scheduling scheme for energy efficient high performance datapath synthesis.
ISCAS (5) 2003: 313-316 |
| 1 | EE | Saraju P. Mohanty,
N. Ranganathan,
Sunil K. Chappidi:
Peak Power Minimization Through Datapath Scheduling.
ISVLSI 2003: 121-126 |
