| 2007 |
|---|
| 5 | EE | Payman Zarkesh-Ha,
Ken Doniger:
Stochastic interconnect layout sensitivity model.
SLIP 2007: 9-14 |
| 2004 |
|---|
| 4 | EE | Payman Zarkesh-Ha,
Ken Doniger,
William Loh,
Peter Bendix:
Prediction of interconnect adjacency distribution: derivation, validation, and applications.
SLIP 2004: 99-106 |
| 2003 |
|---|
| 3 | EE | Payman Zarkesh-Ha,
Ken Doniger,
William Loh,
Dechang Sun,
Rick Stephani,
Gordon Priebe:
A Compact Model for Analysis and Design of On-chip Power Network with Decoupling Capacitors.
ICCD 2003: 84-89 |
| 2 | EE | Payman Zarkesh-Ha,
S. Lakshminarayann,
Ken Doniger,
William Loh,
Peter Wright:
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow.
ISQED 2003: 405-409 |
| 1 | EE | Payman Zarkesh-Ha,
Ken Doniger,
William Loh,
Peter Wright:
Prediction of interconnect pattern density distribution: derivation, validation, and applications.
SLIP 2003: 85-91 |
