| 2006 |
|---|
| 15 | EE | Erik R. Altman,
Sumedh W. Sathaye:
Preface.
IBM Journal of Research and Development 50(2-3): 169-171 (2006) |
| 2001 |
|---|
| 14 | EE | Kemal Ebcioglu,
Erik R. Altman,
Michael Gschwind,
Sumedh W. Sathaye:
Dynamic Binary Translation and Optimization.
IEEE Trans. Computers 50(6): 529-548 (2001) |
| 2000 |
|---|
| 13 | EE | Michael Gschwind,
Kemal Ebcioglu,
Erik R. Altman,
Sumedh W. Sathaye:
Binary translation and architecture convergence issues for IBM system/390.
ICS 2000: 336-347 |
| 12 | | Michael Gschwind,
Erik R. Altman,
Sumedh W. Sathaye,
Paul Ledak,
David Appenzeller:
Dynamic and Transparent Binary Translation.
IEEE Computer 33(3): 54-59 (2000) |
| 11 | EE | Thomas M. Conte,
Sumedh W. Sathaye:
Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility.
IEEE Trans. Computers 49(8): 814-825 (2000) |
| 10 | EE | Thomas M. Conte,
Kishore N. Menezes,
Sumedh W. Sathaye,
Mark C. Toburen:
System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design.
IEEE Trans. VLSI Syst. 8(2): 129-137 (2000) |
| 1999 |
|---|
| 9 | EE | Kemal Ebcioglu,
Erik R. Altman,
Sumedh W. Sathaye,
Michael Gschwind:
Execution-Based Scheduling for VLIW Architectures.
Euro-Par 1999: 1269-1280 |
| 8 | EE | Kemal Ebcioglu,
Erik R. Altman,
Sumedh W. Sathaye,
Michael Gschwind:
Optimizations and Oracle Parallelism with Dynamic Translation.
MICRO 1999: 284- |
| 1998 |
|---|
| 7 | EE | Emre Özer,
Sumedh W. Sathaye,
Kishore N. Menezes,
Sanjeev Banerjia,
Matthew D. Jennings,
Thomas M. Conte:
A Fast Interrupt Handling Scheme for VLIW Processors.
IEEE PACT 1998: 136-141 |
| 6 | | Sanjeev Banerjia,
Sumedh W. Sathaye,
Kishore N. Menezes,
Thomas M. Conte:
MPS: Miss-Path Scheduling for Multiple-Issue Processors.
IEEE Trans. Computers 47(12): 1382-1397 (1998) |
| 1997 |
|---|
| 5 | EE | Kishore N. Menezes,
Sumedh W. Sathaye,
Thomas M. Conte:
Path Prediction for High Issue-Rate Processors.
IEEE PACT 1997: 178-188 |
| 1996 |
|---|
| 4 | EE | Thomas M. Conte,
Sanjeev Banerjia,
Sergei Y. Larin,
Kishore N. Menezes,
Sumedh W. Sathaye:
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.
MICRO 1996: 201-211 |
| 3 | EE | Thomas M. Conte,
Sumedh W. Sathaye,
Sanjeev Banerjia:
A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures.
MICRO 1996: 4-13 |
| 1995 |
|---|
| 2 | EE | Thomas M. Conte,
Kishore N. Menezes,
Sumedh W. Sathaye:
A technique to determine power-efficient, high-performance superscalar processors.
HICSS (1) 1995: 324-333 |
| 1 | EE | Thomas M. Conte,
Sumedh W. Sathaye:
Dynamic rescheduling: a technique for object code compatibility in VLIW architectures.
MICRO 1995: 208-218 |
