2008 | ||
---|---|---|
61 | EE | Balaji V. Iyer, Thomas M. Conte: A Power Model for Register-Sharing Structures. DIPES 2008: 131-142 |
60 | EE | Balaji V. Iyer, Jason A. Poovey, Thomas M. Conte: Energy-aware opcode design. ICCD 2008: 570-576 |
2007 | ||
59 | EE | Thomas M. Conte: Keynote: Insight, Not (Random) Numbers: An Embedded Perspective. HiPEAC 2007: 3 |
58 | EE | Paul D. Bryan, Thomas M. Conte: Combining cluster sampling with single pass methods for efficient sampling regimen design. ICCD 2007: 472-479 |
57 | EE | Paul D. Bryan, Michel C. Rosier, Thomas M. Conte: Reverse State Reconstruction for Sampled Microarchitectural Simulation. ISPASS 2007: 190-199 |
2005 | ||
56 | Thomas M. Conte, Paolo Faraboschi, William H. Mangione-Smith, Walid A. Najjar: Proceedings of the 2005 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2005, San Francisco, California, USA, September 24-27, 2005 ACM 2005 | |
55 | Thomas M. Conte, Nacho Navarro, Wen-mei W. Hwu, Mateo Valero, Theo Ungerer: High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings Springer 2005 | |
54 | EE | Thomas M. Conte: Insight, not (random) numbers. ISPASS 2005: 101 |
53 | EE | Huiyang Zhou, Thomas M. Conte: Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. IEEE Trans. Computers 54(7): 897-912 (2005) |
52 | EE | Emre Özer, Thomas M. Conte: High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. IEEE Trans. Parallel Distrib. Syst. 16(12): 1132-1142 (2005) |
51 | EE | Monther Aldwairi, Thomas M. Conte, Paul D. Franzon: Configurable string matching hardware for speeding up intrusion detection. SIGARCH Computer Architecture News 33(1): 99-107 (2005) |
50 | EE | Saurabh Sharma, Jesse G. Beu, Thomas M. Conte: Spectral prefetcher: An effective mechanism for L2 cache prefetching. TACO 2(4): 423-450 (2005) |
2004 | ||
49 | EE | Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete: Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. IEEE Micro 24(4): 8-9 (2004) |
2003 | ||
48 | Jaime H. Moreno, Praveen K. Murthy, Thomas M. Conte, Paolo Faraboschi: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003 ACM 2003 | |
47 | EE | Huiyang Zhou, Thomas M. Conte: Enhancing memory level parallelism via recovery-free value prediction. ICS 2003: 326-335 |
46 | EE | Huiyang Zhou, Jill Flanagan, Thomas M. Conte: Detecting Global Stride Locality in Value Streams. ISCA 2003: 324-335 |
45 | EE | Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte: Adaptive mode control: A static-power-efficient cache design. ACM Trans. Embedded Comput. Syst. 2(3): 347-372 (2003) |
44 | EE | Chao-ying Fu, Jill T. Bodine, Thomas M. Conte: Modeling Value Speculation: An Optimal Edge Selection Problem. IEEE Trans. Computers 52(3): 277-292 (2003) |
2002 | ||
43 | EE | Huiyang Zhou, Thomas M. Conte: Code Size Efficiency in Global Scheduling for ILP Processors. Interaction between Compilers and Computer Architectures 2002: 79-90 |
42 | EE | Thomas M. Conte: Choosing the Brain(s) of an Embedded System. IEEE Computer 35(7): 106-107 (2002) |
2001 | ||
41 | EE | Emre Özer, Thomas M. Conte, Saurabh Sharma: Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. HiPC 2001: 192-203 |
40 | EE | Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte: Adaptive Mode Control: A Static-Power-Efficient Cache Design. IEEE PACT 2001: 61- |
39 | EE | Huiyang Zhou, Matthew D. Jennings, Thomas M. Conte: Tree Traversal Scheduling: A Global Instruction Scheduling Technique for VLIW/EPIC Processors. LCPC 2001: 223-238 |
2000 | ||
38 | EE | Kim M. Hazelwood, Thomas M. Conte: A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization. IEEE PACT 2000: 71-80 |
37 | EE | Thomas M. Conte, Sumedh W. Sathaye: Properties of Rescheduling Size Invariance for Dynamic Rescheduling-Based VLIW Cross-Generation Compatibility. IEEE Trans. Computers 49(8): 814-825 (2000) |
36 | EE | Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen: System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. VLSI Syst. 8(2): 129-137 (2000) |
1999 | ||
35 | EE | Mouna Nakkar, David G. Bentlage, John Harding, David Schwartz, Paul D. Franzon, Thomas M. Conte: Dynamically Programmable Cache Evaluation and Virtualization. FPGA 1999: 246 |
34 | EE | Sergei Y. Larin, Thomas M. Conte: Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. MICRO 1999: 82-92 |
33 | Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman: Editor's Introduction. International Journal of Parallel Programming 27(5): 325-326 (1999) | |
32 | Thomas M. Conte, Wen-mei W. Hwu, Mark Smotherman: Editors' Introduction. International Journal of Parallel Programming 27(6): 425-426 (1999) | |
1998 | ||
31 | EE | Chao-ying Fu, Matthew D. Jennings, Sergei Y. Larin, Thomas M. Conte: Value Speculation Scheduling for High Performance Processors. ASPLOS 1998: 262-271 |
30 | EE | William A. Havanki, Sanjeev Banerjia, Thomas M. Conte: Treegion Scheduling for Wide Issue Processors. HPCA 1998: 266-276 |
29 | EE | Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte: A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT 1998: 136-141 |
28 | EE | Emre Özer, Sanjeev Banerjia, Thomas M. Conte: Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. MICRO 1998: 308-315 |
27 | Pradip Bose, Thomas M. Conte: Performance Analysis and Its Impact on Design. IEEE Computer 31(5): 41-49 (1998) | |
26 | Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte: MPS: Miss-Path Scheduling for Multiple-Issue Processors. IEEE Trans. Computers 47(12): 1382-1397 (1998) | |
25 | Thomas M. Conte, Mary Ann Hirsch, Wen-mei W. Hwu: Combining Trace Sampling with Single Pass Methods for Efficient Cache Simulation. IEEE Trans. Computers 47(6): 714-720 (1998) | |
1997 | ||
24 | Sanjeev Banerjia, William A. Havanki, Thomas M. Conte: Treegion Scheduling for Highly Parallel Processors. Euro-Par 1997: 1074-1078 | |
23 | EE | Thomas M. Conte, Andrew Wolfe: Combining General-Purpose and Multimedia in One Package: Challenges and Opportunities. HICSS (1) 1997: 708-712 |
22 | EE | Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte: Path Prediction for High Issue-Rate Processors. IEEE PACT 1997: 178-188 |
21 | Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe: Challenges to Combining General-Purpose and Multimedia Processors. IEEE Computer 30(12): 33-37 (1997) | |
20 | Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson: Compilers for Instruction-Level Parallelism. IEEE Computer 30(12): 63-69 (1997) | |
1996 | ||
19 | EE | Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes: Reducing State Loss For Effective Trace Sampling of Superscalar Processors. ICCD 1996: 468-477 |
18 | EE | Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye: Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. MICRO 1996: 201-211 |
17 | EE | Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch: Accurate and Practical Profile-driven Compilation Using the Profile Buffer. MICRO 1996: 36-45 |
16 | EE | Thomas M. Conte, Sumedh W. Sathaye, Sanjeev Banerjia: A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures. MICRO 1996: 4-13 |
15 | Thomas M. Conte: Importance of Profiling and Compatibility. ACM Comput. Surv. 28(4es): 26 (1996) | |
1995 | ||
14 | EE | J. Stan Cox, David P. Howell, Thomas M. Conte: Commercializing profile-driven optimization. HICSS (1) 1995: 221-228 |
13 | EE | Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye: A technique to determine power-efficient, high-performance superscalar processors. HICSS (1) 1995: 324-333 |
12 | EE | Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel: Optimization of Instruction Fetch Mechanisms for High Issue Rates. ISCA 1995: 333-344 |
11 | EE | Thomas M. Conte, Sumedh W. Sathaye: Dynamic rescheduling: a technique for object code compatibility in VLIW architectures. MICRO 1995: 208-218 |
10 | Thomas M. Conte, Wen-mei W. Hwu: Advances in Benchmarking Techniques: New Standards and Quantitative Metrics. Advances in Computers 41: 231-253 (1995) | |
1994 | ||
9 | Thomas M. Conte, Charles E. Gimarc: Fast Simulation of Computer Architectures: Introduction. HICSS (1) 1994: 184 | |
8 | EE | Thomas M. Conte, Burzin A. Patel, J. Stan Cox: Using branch handling hardware to support profile-driven optimization. MICRO 1994: 12-21 |
7 | Wen-mei W. Hwu, Thomas M. Conte: The Susceptibility of Programs to Context Switching. IEEE Trans. Computers 43(9): 994-1003 (1994) | |
1993 | ||
6 | Thomas M. Conte, William H. Mangione-Smith: Determining Cost-Effective Multiple Issue Processor Designs. ICCD 1993: 94-101 | |
5 | William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu: The Effect of Code Expanding Optimizations on Instruction Cache Design. IEEE Trans. Computers 42(9): 1045-1057 (1993) | |
1992 | ||
4 | EE | Thomas M. Conte: Tradeoffs in processor/memory interfaces for superscalar processors. MICRO 1992: 202-205 |
1991 | ||
3 | Thomas M. Conte, Wen-mei W. Hwu: Benchmark Characterization. IEEE Computer 24(1): 48-56 (1991) | |
1989 | ||
2 | EE | Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang: Comparing Software and Hardware Schemes For Reducing the Cost of Branches. ISCA 1989: 224-233 |
1 | Wen-mei W. Hwu, Thomas M. Conte: A Simulation Study of Simultaneous Vector Prefetch Performance in Multiprocessor Memory Subsystems (Extended Abstract). SIGMETRICS 1989: 227 |