2005 |
12 | EE | Philippe Royannez,
Hugh Mair,
Franck Dahan,
Mike Wagner,
Mark Streeter,
Laurent Bouetel,
Joel Blasquez,
H. Clasen,
G. Semino,
Julie Dong,
D. Scott,
B. Pitts,
Claudine Raibaut,
Uming Ko:
A design platform for 90-nm leakage reduction techniques.
DAC 2005: 549-550 |
2000 |
11 | EE | Uming Ko,
Poras T. Balsara:
High-performance energy-efficient D-flip-flop circuits.
IEEE Trans. VLSI Syst. 8(1): 94-98 (2000) |
1999 |
10 | EE | Uming Ko,
Mike McMahan,
Edgar Auslander:
DSP for the Third Generation Wireless Communications.
ICCD 1999: 516-520 |
1998 |
9 | EE | Uming Ko,
Poras T. Balsara,
Ashwini K. Nanda:
Energy optimization of multilevel cache architectures for RISC and CISC processors.
IEEE Trans. VLSI Syst. 6(2): 299-308 (1998) |
1997 |
8 | | David Li,
Andrew Pua,
Pranjal Srivastava,
Uming Ko:
A Repeater Optimization Methodology for Deep Sub-Micron, High Performance Processors.
ICCD 1997: 726-731 |
7 | EE | June Jiang,
Kan Lu,
Uming Ko:
High-performance, low-power design techniques for dynamic to static logic interface.
ISLPED 1997: 12-17 |
6 | EE | Uming Ko,
Andrew Pua,
Anthony M. Hill,
Pranjal Srivastava:
Hybrid dual-threshold design techniques for high-performance processors with low-power features.
ISLPED 1997: 307-311 |
1996 |
5 | EE | Uming Ko,
Anthony M. Hill,
Poras T. Balsara:
Design techniques for high performance, energy efficient control logic.
ISLPED 1996: 97-100 |
1995 |
4 | EE | Uming Ko,
Poras T. Balsara,
Ashwini K. Nanda:
Energy optimization of multi-level processor cache architectures.
ISLPD 1995: 45-49 |
3 | EE | Uming Ko,
T. Balsara,
Wai Lee:
Low-power design techniques for high-performance CMOS adders.
IEEE Trans. VLSI Syst. 3(2): 327-333 (1995) |
2 | EE | Uming Ko,
Poras T. Balsara:
Short-circuit power driven gate sizing technique for reducing power dissipation.
IEEE Trans. VLSI Syst. 3(3): 450-455 (1995) |
1985 |
1 | | Uming Ko,
Dinesh G. Patel,
Francois J. Henley:
Contactless VLSI Laser Probing.
ITC 1985: 930-937 |