2009 |
10 | EE | Kenneth L. Rice,
Tarek M. Taha,
Christopher N. Vutsinas:
Scaling analysis of a neocortex inspired cognitive model on the Cray XD1.
The Journal of Supercomputing 47(1): 21-43 (2009) |
2008 |
9 | EE | Christopher N. Vutsinas,
Tarek M. Taha,
Kenneth L. Rice:
A neocortex model implementation on reconfigurable logic with streaming memory.
IPDPS 2008: 1-8 |
8 | EE | Tarek M. Taha,
D. Scott Wills:
An Instruction Throughput Model of Superscalar Processors.
IEEE Trans. Computers 57(3): 389-403 (2008) |
2007 |
7 | EE | Kenneth L. Rice,
Christopher N. Vutsinas,
Tarek M. Taha:
A preliminary investigation of a neocortex model implementation on the Cray XD1.
SC 2007: 2 |
2006 |
6 | EE | Clint W. Smullen,
Tarek M. Taha:
PSATSim: an interactive graphical superscalar architecture simulator for power and performance analysis.
WCAE 2006: 3 |
2005 |
5 | EE | Kiruthika Selvamani,
Tarek M. Taha:
Estimating critical region parallelism to guide platform retargeting.
ACM Southeast Regional Conference (1) 2005: 168-173 |
2003 |
4 | EE | Tarek M. Taha,
D. Scott Wills:
An Instruction Throughput Model of Superscalar Processors.
IEEE International Workshop on Rapid System Prototyping 2003: 156-163 |
2002 |
3 | EE | Linda M. Wills,
Tarek M. Taha,
Lewis B. Baumstark Jr.,
D. Scott Wills:
Estimating Potential Parallelism for Platform Retargeting.
WCRE 2002: 55-64 |
2000 |
2 | EE | Sek M. Chai,
Tarek M. Taha,
D. Scott Wills,
James D. Meindl:
Heterogeneous architecture models for interconnect-motivated system design.
IEEE Trans. VLSI Syst. 8(6): 660-670 (2000) |
1999 |
1 | EE | Lucian Codrescu,
Mondira Deb Pant,
Tarek M. Taha,
John Eble,
D. Scott Wills,
James D. Meindl:
Exploring Microprocessor Architectures for Gigascale Integration.
ARVLSI 1999: 242-255 |