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K. Wayne Current

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2005
19EEMarko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija: A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. PATMOS 2005: 724-732
2002
18EEYongjian Brandon Guo, K. Wayne Current: Voltage Comparator Circuits for Multiple-Valued CMOS Logic. ISMVL 2002: 67-
2000
17EEDan Olson, K. Wayne Current: Hardware Implementation of ``Supplementary Symmetrical Logic Circuit Structure'' Concepts. ISMVL 2000: 371-376
16EEK. Wayne Current: Design of a Quaternary Latch Circuit Using a Binary CMOS RS Latch. ISMVL 2000: 377-381
15EEDragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current: Clocked CMOS adiabatic logic with integrated single-phase power-clock supply. IEEE Trans. VLSI Syst. 8(4): 460-463 (2000)
1997
14EEDragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current: Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results. ISLPED 1997: 323-327
1996
13EEK. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic: Low-Energy Logic Circuit Techniques for Multiple-Valued Logic. ISMVL 1996: 86-
1995
12EEK. Wayne Current: Memory Circuits for Multiple-Valued Logic Voltage Signals. ISMVL 1995: 52-57
1994
11 Wei-Shang Chu, K. Wayne Current: Quaternary Multiplier Circuit. ISMVL 1994: 15-18
1993
10 K. Wayne Current, Jim Parker, Wes Hardaker: Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICs. ISCAS 1993: 2090-2093
9 K. Wayne Current: Multiple Valued Logic: Current-Mode CMOS Circuits. ISMVL 1993: 176-181
1992
8 K. Wayne Current: A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter Circuit. ISMVL 1992: 229-234
1991
7 K. Wayne Current, M. E. Hurlston: A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory Circuit. ISMVL 1991: 196-202
1990
6 K. Wayne Current: A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent Latch. ISMVL 1990: 168-173
1986
5 James L. Mangin, K. Wayne Current: Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder Circuits. IEEE Trans. Computers 35(2): 157-161 (1986)
1980
4 K. Wayne Current: High Density Integrated Computing Circuitry with Multiple Valued Logic. IEEE Trans. Computers 29(2): 191-195 (1980)
3 K. Wayne Current: Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full Adders. IEEE Trans. Computers 29(5): 400-403 (1980)
2 K. Wayne Current: A High Data-Rate Digital Output Correlator Design. IEEE Trans. Computers 29(5): 403-405 (1980)
1979
1 K. Wayne Current, Douglas A. Mow: Implementing Parallel Counters with Four-Valued Threshold Logic. IEEE Trans. Computers 28(3): 200-204 (1979)

Coauthor Index

1Marko Aleksic [19]
2Wei-Shang Chu [11]
3Yongjian Brandon Guo [18]
4Wes Hardaker [10]
5M. E. Hurlston [7]
6Dragan Maksimovic [13] [14] [15]
7James L. Mangin [5]
8Douglas A. Mow [1]
9Nikola Nedovic [19]
10Borivoje Nikolic [14] [15]
11Vojin G. Oklobdzija [13] [14] [15] [19]
12Dan Olson [17]
13Jim Parker [10]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)