| 2003 |
|---|
| 6 | EE | Stephen V. Kosonocky,
Azeez J. Bhavnagarwala,
Kenneth Chin,
George Gristede,
Anne-Marie Haen,
Wei Hwang,
Mark B. Ketchen,
Suhwan Kim,
Daniel R. Knebel,
Kevin W. Warren,
Victor V. Zyuban:
Low-power circuits and technology for wireless digital systems.
IBM Journal of Research and Development 47(2-3): 283-298 (2003) |
| 2001 |
|---|
| 5 | | Azeez J. Bhavnagarwala,
Stephen V. Kosonocky,
James D. Meindl:
Interconnect-centric Array Architectures for Minimum SRAM Access Time.
ICCD 2001: 400-405 |
| 2000 |
|---|
| 4 | EE | Azeez J. Bhavnagarwala,
Blanca Austin,
Ashok Kapoor,
James D. Meindl:
CMOS system-on-a-chip voltage scaling beyond 50nm.
ACM Great Lakes Symposium on VLSI 2000: 7-12 |
| 3 | EE | Azeez J. Bhavnagarwala,
Blanca Austin,
Keith A. Bowman,
James D. Meindl:
A minimum total power methodology for projecting limits on CMOS GSI.
IEEE Trans. VLSI Syst. 8(3): 235-251 (2000) |
| 1998 |
|---|
| 2 | EE | Azeez J. Bhavnagarwala,
Blanca Austin,
James D. Meindl:
Minimum supply voltage for bulk Si CMOS GSI.
ISLPED 1998: 100-102 |
| 1996 |
|---|
| 1 | EE | Azeez J. Bhavnagarwala,
Vivek De,
Blanca Austin,
James D. Meindl:
Circuit techniques for low-power CMOS GSI.
ISLPED 1996: 193-196 |
