Kishore N. Menezes

2000
12	EE	Jay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce: The Intel IA-64 Compiler Code Generator. IEEE Micro 20(5): 44-53 (2000)
11	EE	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye, Mark C. Toburen: System-level power consumption modeling and tradeoff analysis techniques for superscalar processor design. IEEE Trans. VLSI Syst. 8(2): 129-137 (2000)
10	EE	Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey: Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs. J. Instruction-Level Parallelism 2: (2000)
1999
9	EE	Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey: Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. MICRO 1999: 262-271
1998
8	EE	Emre Özer, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte: A Fast Interrupt Handling Scheme for VLIW Processors. IEEE PACT 1998: 136-141
7		Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte: MPS: Miss-Path Scheduling for Multiple-Issue Processors. IEEE Trans. Computers 47(12): 1382-1397 (1998)
1997
6	EE	Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte: Path Prediction for High Issue-Rate Processors. IEEE PACT 1997: 178-188
1996
5	EE	Thomas M. Conte, Mary Ann Hirsch, Kishore N. Menezes: Reducing State Loss For Effective Trace Sampling of Superscalar Processors. ICCD 1996: 468-477
4	EE	Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye: Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. MICRO 1996: 201-211
3	EE	Thomas M. Conte, Kishore N. Menezes, Mary Ann Hirsch: Accurate and Practical Profile-driven Compilation Using the Profile Buffer. MICRO 1996: 36-45
1995
2	EE	Thomas M. Conte, Kishore N. Menezes, Sumedh W. Sathaye: A technique to determine power-efficient, high-performance superscalar processors. HICSS (1) 1995: 324-333
1	EE	Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel: Optimization of Instruction Fetch Mechanisms for High Issue Rates. ISCA 1995: 333-344

Coauthor Index

1	Sanjeev Banerjia	[4] [7] [8]
2	Jay Bharadwaj	[9] [10] [12]
3	William Y. Chen	[12]
4	Weihaw Chuang	[12]
5	Thomas M. Conte	[1] [2] [3] [4] [5] [6] [7] [8] [11]
6	Mary Ann Hirsch	[3] [5]
7	Gerolf Hoflehner	[12]
8	Matthew D. Jennings	[8]
9	Sergei Y. Larin	[4]
10	Chris McKinsey	[9] [10]
11	Patrick M. Mills	[1]
12	Kalyan Muthukumar	[12]
13	Emre Özer	[8]
14	Burzin A. Patel	[1]
15	Jim Pierce	[12]
16	Sumedh W. Sathaye	[2] [4] [6] [7] [8] [11]
17	Mark C. Toburen	[11]