DSD 2003:
Belek-Antalya,
Turkey
2003 Euromicro Symposium on Digital Systems Design (DSD 2003), Architectures, Methods and Tools, 3-5 September 2003, Belek-Antalya, Turkey.
IEEE Computer Society 2003, ISBN 0-7695-2003-0 BibTeX
Keynote Speeches
Processor and Memory Architectures
Synthesis (HL,
LS,
PS)
Processor and Memory Architectures
Synthesis (HL,
LS,
PS)
Processor and Memory Architectures
Synthesis (HL,
LS,
PS)
Special Architectures
- Peter Petrov, Alex Orailoglu:
Low-power Branch Target Buffer for Application-Specific Embedded Processors.
158-165
Electronic Edition (link) BibTeX
- Philip K. F. Hölzenspies, Erik Schepers, Wouter Bach, Mischa Jonker, Bart Sikkes, Gerard J. M. Smit, Paul J. M. Havinga:
A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole Routing.
166-172
Electronic Edition (link) BibTeX
- Marco Bera, Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti:
A Development and Simulation Environment for a Floating Point Operations FPGA Based Accelerator.
173-179
Electronic Edition (link) BibTeX
- Tang Lei, Shashi Kumar:
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture.
180-189
Electronic Edition (link) BibTeX
System-on-a-Chip
Special Architectures
Synthesis (HL,
LS,
PS)
- Amirali Baniasadi:
Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered Architectures.
240-247
Electronic Edition (link) BibTeX
- Michal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba:
NOAH, a tool for argument reduction, serial and parallel decomposition of decision tables.
248-254
Electronic Edition (link) BibTeX
- Valery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida:
Design Tools and Reusable Libraries for FPGA-Based Digital Circuits.
255-263
Electronic Edition (link) BibTeX
- Karthikeyan Bhasyam, Kia Bazargan:
HW/SW Codesign Incorporating Edge Delays Using Dynamic Programming.
264-271
Electronic Edition (link) BibTeX
- Fatih Kocan:
Reconfigurable Randomized K-way Graph Partitioning.
272-278
Electronic Edition (link) BibTeX
- Bharath Radhakrishnan, Muthukumar Venkatesan:
Multiple Voltage and Frequency Scheduling for Power Minimization.
279-285
Electronic Edition (link) BibTeX
Special Architectures
System-on-a-Chip (2) and Validation/Verification
Applications of (Embedded) Digital Systems
- Filip Traugott, Kim Andersson, Andreas Löfgren, Lennart Lindh:
Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator Algorithm.
334-337
Electronic Edition (link) BibTeX
- Margarita Amor, Montserrat Bóo, Ángel del Río, Michael Wand, Wolfgang Straßer:
A New Algorithm for High-Speed Projection in Point Rendering Applications.
338-345
Electronic Edition (link) BibTeX
- Marco De Marinis, Luca Fanucci, A. Giambastiani, Alessandro Renieri, A. Rocchi, Christian Rosadini, Claudio Sicilia, Daniele Sicilia:
Sensor Platform Design for Automotive Applications.
346-355
Electronic Edition (link) BibTeX
Specification and Modeling
Applications of (Embedded) Digital Systems
Applications of (Embedded) Digital Systems
Specification and Modeling
Poster Papers
- S. T. G. S. Ramakrishna, H. S. Jamadagni:
Analytical Bounds on the Threads in IXP1200 Network Processor.
426-429
Electronic Edition (link) BibTeX
- Gregor Papa, Jurij Silc:
Concurrent Operation Scheduling and Unit Allocation with an Evolutionary Technique.
430-433
Electronic Edition (link) BibTeX
- Juan Manuel García Chamizo, Jerónimo Mora Pascual, Higinio Mora Mora:
Exact Numerical Processing.
434-437
Electronic Edition (link) BibTeX
- Nadia Nedjah, Luiza de Macedo Mourelle:
Stochastic Reconfigurable Hardware for Neural Networks.
438-442
Electronic Edition (link) BibTeX
- Radoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha:
An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAs.
443-446
Electronic Edition (link) BibTeX
- Jouni Riihimäki, Väinö Helminen, Kimmo Kuusilinna, Timo D. Hämäläinen:
Distributing SoC Simulations over a Network of Computers.
447-450
Electronic Edition (link) BibTeX
- Petr Fiser, Jan Hlavicka, Hana Kubatova:
FC-Min: A Fast Multi-Output Boolean Minimizer.
451-454
Electronic Edition (link) BibTeX
- Václav Dvorák, Vladimír Kutálek:
A Methodology for Designing Communication Architectures for Multiprocessor SoCs.
455-458
Electronic Edition (link) BibTeX
- Guangyu Chen, Guangyu Chen, Ismail Kadayif, Wei Zhang, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer:
Compiler-Directed Management of Instruction Accesses.
459-462
Electronic Edition (link) BibTeX
- Zdenek Kotásek, Daniel Mika, Josef Strnadel:
Test scheduling for embedded systems.
463-467
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:07:28 2009
by Michael Ley (ley@uni-trier.de)
