VLSI-SoC 2006:
Nice,
France
IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006.
IEEE 2006 BibTeX
- Jacques Benkowski:
The system is really in the SoC : new investment opportunities.
Electronic Edition (link) BibTeX
- A. Domman:
An overview of where the fields of SoCs, HDI and MEMS are heading to and how to characterize them.
Electronic Edition (link) BibTeX
- Jean-Pierre Schoellkopf:
Design challenges for the 45 nm node and below.
Electronic Edition (link) BibTeX
- Shekhar Borkar:
Introduction to panel discussion Probabilistic & statistical design - the wave of the future.
Electronic Edition (link) BibTeX
- Bilge E. S. Akgul, Lakshmi N. Chakrapani, Pinar Korkmaz, Krishna V. Palem:
Probabilistic CMOS Technology: A Survey and Future Directions.
1-6
Electronic Edition (link) BibTeX
- Alain J. Martin:
Can Asynchronous Techniques Help the SoC Designer?
7-11
Electronic Edition (link) BibTeX
- Laurent Fesquet, Bertrand Folco, M. Steiner, Marc Renaudin:
State-holding in Look-Up Tables: application to asynchronous logic.
12-17
Electronic Edition (link) BibTeX
- Peter Malík, Marcel Baláz, Tomás Pikula, Martin Simlastík:
MDCT IP Core Generator with Architectural Model Simulation.
18-23
Electronic Edition (link) BibTeX
- Marco Giorgetta, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini:
A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures.
24-29
Electronic Edition (link) BibTeX
- Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro:
Automatic Dataflow Execution with Reconfiguration and Dynamic Instruction Merging.
30-35
Electronic Edition (link) BibTeX
- Sam Kavusi, Kunal Ghosh, Abbas El Gamal:
Architectures for High Dynamic Range, High Speed Image Sensor Readout Circuits.
36-41
Electronic Edition (link) BibTeX
- Shoji Kawahito:
Circuit and Device Technologies for CMOS functional Image Sensors.
42-47
Electronic Edition (link) BibTeX
- Robert Henderson, Bruce Rae, David Renshaw, E. Charbon:
Oversampled Time Estimation Techniques for Precision Photonic Detectors.
48-51
Electronic Edition (link) BibTeX
- Arnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi:
Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.
52-57
Electronic Edition (link) BibTeX
- Ramachandruni Venkata Kamala, M. B. Srinivas:
High-Throughput Montgomery Modular Multiplication.
58-62
Electronic Edition (link) BibTeX
- Sinan Yalcin, Ilker Hamzaoglu:
A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation.
63-67
Electronic Edition (link) BibTeX
- Hsin-Chou Chi, Chia-Ming Wu:
An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures.
68-73
Electronic Edition (link) BibTeX
- Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto:
Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow.
74-79
Electronic Edition (link) BibTeX
- Chris Bartels, Jos Huisken, Kees Goossens, Patrick Groeneveld, Jef L. van Meerbergen:
Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.
80-85
Electronic Edition (link) BibTeX
- Sanghun Lee, Chanho Lee:
A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes.
86-91
Electronic Edition (link) BibTeX
- Hamid Shojaei, Mohammad Sayyaran:
Signal Coverage Computation in Formal Verification.
92-97
Electronic Edition (link) BibTeX
- Justin Xu, Cheng-Chew Lim:
Modelling Heterogeneous Interactions in SoC Verification.
98-103
Electronic Edition (link) BibTeX
- Shih-Chieh Wu, Chun-Yao Wang:
PEACH: A Novel Architecture for Probabilistic Combinational Equivalence Checking.
104-109
Electronic Edition (link) BibTeX
- Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.:
A Fast SAT Solver Strategy Based on Negated Clauses.
110-115
Electronic Edition (link) BibTeX
- Chin-Cheng Kuo, Chien-Nan Jimmy Liu:
On Efficient Behavioral Modeling to Accurately Predict Supply Noise Effects of PLL Designs in Real Systems.
116-121
Electronic Edition (link) BibTeX
- Luís Guerra e Silva, Zhenhai Zhu, Joel R. Phillips, L. Miguel Silveira:
Variation-Aware, Library Compatible Delay Modeling Strategy.
122-127
Electronic Edition (link) BibTeX
- Renato Fernandes Hentschke, Sandro Sawicki, Marcelo de Oliveira Johann, Ricardo Augusto da Luz Reis:
An Algorithm for I/O Partitioning Targeting 3D Circuits and Its Impact on 3D-Vias.
128-133
Electronic Edition (link) BibTeX
- Vagner S. Rosa, Eduardo Costa, Sergio Bampi:
A VHDL Generation Tool for Optimized Parallel FIR Filters.
134-139
Electronic Edition (link) BibTeX
- Pablo Garcia Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli:
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.
140-145
Electronic Edition (link) BibTeX
- Giovanni Beltrame, Donatella Sciuto, Cristina Silvano, Pierre G. Paulin, Essaid Bensoudane:
An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures.
146-151
Electronic Edition (link) BibTeX
- Derin Derin Harmanci, Nuria Pazos, Paolo Ienne, Yusuf Leblebici:
A Predictable Communication Scheme for Embedded Multiprocessor Systems.
152-157
Electronic Edition (link) BibTeX
- Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo:
Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.
158-163
Electronic Edition (link) BibTeX
- Ulrich Bockelmann:
Detecting DNA by field effect transistor arrays.
164-168
Electronic Edition (link) BibTeX
- Carlotta Guiducci, Claudio Stagni, M. Brocchi, Massimo Lanzoni, Bruno Riccò, A. Nascetti, D. Caputo, G. de Cesare:
Innovative Optoelectronic Approaches to Biomolecular Analysis with Arrays of Silicon Devices.
169-174
Electronic Edition (link) BibTeX
- Bert Gyselinckx, R. Vullers, C. Van Hoof, Julien Ryckaert, R. F. Yazicioglu, P. Fiorini, V. Leonov:
Human++: Emerging Technology for Body Area Networks.
175-180
Electronic Edition (link) BibTeX
- Alin Razafindraibe, Philippe Maurine, Michel Robert, Marc Renaudin:
Security evaluation of dual rail logic against DPA attacks.
181-186
Electronic Edition (link) BibTeX
- Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro:
A low power high performance CMOS voltage-mode quaternary full adder.
187-191
Electronic Edition (link) BibTeX
- Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.
192-197
Electronic Edition (link) BibTeX
- Motoki Amagasaki, Takurou Shimokawa, Kazunori Matsuyama, Ryoichi Yamaguchi, Hideaki Nakayama, Naoto Hamabe, Masahiro Iida, Toshinori Sueyoshi:
Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable Device.
198-203
Electronic Edition (link) BibTeX
- Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis:
Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.
204-209
Electronic Edition (link) BibTeX
- Senthamaraikannan Raghunath, Syed M. Aziz:
High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor.
210-215
Electronic Edition (link) BibTeX
- Xue-mi Zhao, Zhiying Wang, Hongyi Lu, Kui Dai:
A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.
216-221
Electronic Edition (link) BibTeX
- Sujan Pandey, Nurten Utlu, Manfred Glesner:
Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.
222-227
Electronic Edition (link) BibTeX
- Wagston T. Staehler, Eduardo A. Berriel, Altamiro Amadeu Susin, Sergio Bampi:
Architecture of an HDTV Intraframe Predictor for a H.264 Decoder.
228-233
Electronic Edition (link) BibTeX
- Stéphane Badel, Ilhan Hatirnaz, Yusuf Leblebici, Elizabeth J. Brauer:
Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells.
234-238
Electronic Edition (link) BibTeX
- M. Shah, D. Nagchoudhuri:
BIST Scheme for Low Heat Dissipation and Reduced Test Application Time.
239-244
Electronic Edition (link) BibTeX
- Ron Press, Jay Jahangiri:
The Demand and Practical Approach for 100x Test Compression.
245-250
Electronic Edition (link) BibTeX
- Ravindra V. Kshirsagar, Rajendra M. Patrikar:
Design of a Reconfigurable Multiprocessor Core for Higher Performance and Reliability of Embedded Systems.
251-254
Electronic Edition (link) BibTeX
- Shampa Chakraverty, Arvind Batra, Aman Rathi:
Directed Convergence Heuristic: A fast & novel approach to Steiner Tree Construction.
255-260
Electronic Edition (link) BibTeX
- Beate Muranko, Rolf Drechsler:
Technical Documentation of Software and Hardware in Embedded Systems.
261-266
Electronic Edition (link) BibTeX
- Ramon Tortosa Navas, Antonio Aceituno, José Manuel de la Rosa, Francisco V. Fernández, Ángel Rodríguez-Vázquez:
Design of a 1.2-V 130nm CMOS 13-bit@40MS/s Cascade 2-2-1 Continuous-Time Sigma-Delta Modulator.
267-271
Electronic Edition (link) BibTeX
- Yngvar Berg, Omid Mirmotahari, Snorre Aunet:
Pseudo Floating-Gate Inverter with Feedback Control.
272-277
Electronic Edition (link) BibTeX
- Hanene Ben Fradj, Cécile Belleudy, Michel Auguin:
Main Memory Energy Optimization for Multi-Task Applications.
278-283
Electronic Edition (link) BibTeX
- Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
EXOR Projected Sum of Products.
284-289
Electronic Edition (link) BibTeX
- Ittetsu Taniguchi, Kyoko Ueda, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai:
Task Partitioning Oriented Architecture Exploration Method for Dynamic Reconfigurable Architectures.
290-295
Electronic Edition (link) BibTeX
- Sujan Pandey, Tudor Murgan, Manfred Glesner:
Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis.
296-301
Electronic Edition (link) BibTeX
- Tudor Murgan, O. Mitrea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner:
Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.
302-307
Electronic Edition (link) BibTeX
- Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara:
A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.
308-313
Electronic Edition (link) BibTeX
- Margrit R. Krug, Marcelo Lubaszewski, Marcelo de Souza Moraes:
Improving ATPG Gate-Level Fault Coverage by using Test Vectors generated from Behavioral HDL Descriptions.
314-319
Electronic Edition (link) BibTeX
- Ahcène Bounceur, Salvador Mir, Luís Rolíndez, Emmanuel Simeu:
CAT platform for analogue and mixed-signal test evaluation and optimization.
320-325
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- Livier Lizzarraga, Salvador Mir, Gilles Sicard, Ahcène Bounceur:
Study of a BIST Technique for CMOS Active Pixel Sensors.
326-331
Electronic Edition (link) BibTeX
- Subhasish Mitra, Ming Zhang, Norbert Seifert, T. M. Mak, Kee Sup Kim:
Soft Error Resilient System Design through Error Correction.
332-337
Electronic Edition (link) BibTeX
- Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel:
Organic Computing at the System on Chip Level.
338-341
Electronic Edition (link) BibTeX
- Antonis Papanikolaou, Miguel Miranda, Hua Wang, Francky Catthoor, M. Satyakiran, Pol Marchal, Ben Kaczer, C. Bruynseraede, Zsolt Tokei:
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
342-347
Electronic Edition (link) BibTeX
- Xiaopeng Yu, Manh Anh Do, Jianguo Ma, Kiat Seng Yeo:
A New Phase Noise Model for TSPC based divider.
348-351
Electronic Edition (link) BibTeX
- Shan Jiang, Manh Anh Do, Kiat Seng Yeo:
A 200-MHz CMOS Mixed-Mode Sample-and-Hold Circuit for Pipelined ADCs.
352-356
Electronic Edition (link) BibTeX
- Yue-Fang Kuo, Ro-Min Weng, Chun-Yu Liu:
A 5.4-GHz Low-Power Swallow-Conterless Frequency Synthesizer with a Nonliear PFD.
357-360
Electronic Edition (link) BibTeX
- Jeff Brateman, Changjiu Xian, Yung-Hsiang Lu:
Energy-Effcient Scheduling for Autonomous Mobile Robots.
361-366
Electronic Edition (link) BibTeX
- Se Hun Kim, Vincent John Mooney:
Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.
367-372
Electronic Edition (link) BibTeX
- Rodrigo M. Passos, José Augusto Miranda Nacif, Raquel A. F. Mini, Antonio Alfredo Ferreira Loureiro, Antônio Otávio Fernandes, Claudionor José Nunes Coelho Jr.:
System-level Dynamic Power Management Techniques for Communication Intensive Devices.
373-378
Electronic Edition (link) BibTeX
- Zeynep Toprak Deniz, Yusuf Leblebici, Eric A. Vittoz:
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of Analog Computation.
379-384
Electronic Edition (link) BibTeX
- K. Schultz, K. Paranjape:
SOC Debug Challenges and Tools.
385-390
Electronic Edition (link) BibTeX
- Pierre Vanhauwaert, Régis Leveugle, Philippe Roche:
Reduced Instrumentation and Optimized Fault Injection Control for Dependability Analysis.
391-396
Electronic Edition (link) BibTeX
- Yann Oddos, Katell Morin-Allory, Dominique Borrione:
On-Line Test Vector Generation from Temporal Constraints Written in PSL.
397-402
Electronic Edition (link) BibTeX
- Nabil Badereddine, Patrick Girard, Serge Pravossoudovitch, Christian Landrault, Arnaud Virazel, Hans-Joachim Wunderlich:
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing.
403-408
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:46:40 2009
by Michael Ley (ley@uni-trier.de)
