DSD 2004:
Rennes,
France
2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August - 3 September 2004, Rennes, France.
IEEE Computer Society 2004, ISBN 0-7695-2203-3 BibTeX
Keynote Speeches
Invited Papers
Processor and Memory Architectures (S1)
Synthesis (HL,
LS,
PS) (S6)
Processor and Memory Architectures (S2)
Synthesis (HL,
LS,
PS) (S7)
- Mariusz Rawski, Henry Selvaraj, Pawel Morawiecki:
Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary Algorithms.
136-143
Electronic Edition (link) BibTeX
- Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke:
Cost-Efficient Implementation of Adaptive Finite State Machines.
144-151
Electronic Edition (link) BibTeX
- Petr Fiser, Hana Kubatova:
Boolean Minimizer FC-Min: Coverage Finding Process.
152-159
Electronic Edition (link) BibTeX
- Lech Józwiak, Dominik Gawlowski, Aleksander Slusarczyk:
An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment Methods.
160-167
Electronic Edition (link) BibTeX
- Görschwin Fey, Junhao Shi, Rolf Drechsler:
BDD Circuit Optimization for Path Delay Fault Testability.
168-172
Electronic Edition (link) BibTeX
Applications of (Embedded) Digital Systems (S15)
- Pasquale Ciao, Giulio Colavolpe, Luca Fanucci:
A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code Decoder.
174-181
Electronic Edition (link) BibTeX
- Luca Fanucci, Riccardo Locatelli, Esa Petri:
VLSI Design of a Digital RFI Cancellation Scheme for VDSL Transceivers.
182-189
Electronic Edition (link) BibTeX
- Jayapreetha Natesan, Damu Radhakrishnan:
Shift Invert Coding (SINV) for Low Power VLSI.
190-194
Electronic Edition (link) BibTeX
- Jeffrey McFiggins, Marie Yvanoff, Jayanti Venkataraman:
Generalized Analytical Model for the Design of Irregularly Shaped Power Planes and Passives in Mixed Signal Applications.
195-199
Electronic Edition (link) BibTeX
- Jussi Roivainen, Jukka Rautio:
IP-Block Based Integration of Very High Performance WLAN Modem.
200-207
Electronic Edition (link) BibTeX
DSP + MISC (S17)
Special Architectures (S5)
Processor and Memory Architectures (S3)
Synthesis (S9)
SOC (S13)
Special Architectures (S4)
Specification and Modeling (S10)
- Daniel Karlsson, Petru Eles, Zebo Peng:
A Formal Verification Methodology for IP-based Designs.
372-379
Electronic Edition (link) BibTeX
- Haridimos T. Vergos, Costas Efstathiou:
Diminished-1 Modulo 2n + 1 Squarer Design.
380-386
Electronic Edition (link) BibTeX
- Miroslaw Jablonski, Marek Gorgon:
Handel-C implementation of Classical Component Labelling Algorithm.
387-393
Electronic Edition (link) BibTeX
- David Elléouet, Nathalie Julien, Dominique Houzet, J.-G. Cousin, Eric Martin:
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGA.
394-401
Electronic Edition (link) BibTeX
- Daniel Dietterle, Jerzy Ryman, Kai F. Dombrowski, Rolf Kraemer:
Mapping of High-Level SDL Models to Efficient Implementations for TinyOS.
402-406
Electronic Edition (link) BibTeX
Validation / Verification (S12)
- Abdil Rashid Mohamed, Zebo Peng, Petru Eles:
A Heuristic for Wiring-Aware Built-In Self-Test Synthesis.
408-415
Electronic Edition (link) BibTeX
- Alexander V. Drozd, R. Al-Azzeh, J. V. Drozd, M. V. Lobachev:
The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated Data.
416-423
Electronic Edition (link) BibTeX
- Iosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha:
Scene Management Models and Overlap Tests for Tile-Based Rendering.
424-431
Electronic Edition (link) BibTeX
- Piotr Gawkowski, Janusz Sosnowski:
Evaluation of Transient Fault Susceptibility in Microprocessor Systems.
432-439
Electronic Edition (link) BibTeX
- Vladimir Hahanov, Irina Hahanova, Stanley Hyduke:
Topological BDP Fault Simulation Method.
440-443
Electronic Edition (link) BibTeX
- Hamid Shojaei, Habib Ghayoumi:
Techniques for Formal Verification of Digital Systems: A System Approach.
444-449
Electronic Edition (link) BibTeX
Applications of (Embedded) Digital Systems (S16)
Specification and Modeling (S11)
SOC (S14)
Special Architectures (S5)
MISC + Algorithm (S18)
Sensor Networks (S19)
Poster Papers
- Abey Abraham Cohen:
Addressing architecture for Brain-like Massively Parallel Computers.
594-597
Electronic Edition (link) BibTeX
- Soyeb Alli, Chris Bailey:
A Mechanism for Implementing Precise Exceptions in Pipelined Processors.
598-602
Electronic Edition (link) BibTeX
- Hafiz Md. Hasan Babu, Moinul Islam Zaber, Md. Mazder Rahman, Md. Rafiqul Islam:
Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic.
603-606
Electronic Edition (link) BibTeX
- Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya:
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy.
607-610
Electronic Edition (link) BibTeX
- Mohammad K. Akbari, Ali Jahanian, Mohsen Naderi, Bahman Javadi:
Area Efficient, Low Power and Robust Design for Add-Compare-Select Units.
611-614
Electronic Edition (link) BibTeX
- Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis:
A Static Low-Power, High-Performance 32-bit Carry Skip Adder.
615-619
Electronic Edition (link) BibTeX
- J. D. Kranthi Kumar, S. Srinivasan:
A Novel VLSI Architecture to Implement Region Merging Algorithm for Image Segmentation.
620-623
Electronic Edition (link) BibTeX
- Maria J. Avedillo, José M. Quintana:
A Threshold Logic Synthesis Tool for RTD Circuits.
624-627
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:07:28 2009
by Michael Ley (ley@uni-trier.de)
